| Start | End | Peony Ballroom |
|---|---|---|
| 08:30 | 09:00 | Opening |
| 09:00 | 09:40 | Keynote: Prof. Benini, Luca (Università di Bologna) "Designing Open Platforms for the Embodied AI Era" |
| 09:40 | 10:20 | Keynote: Prof. Yeo, Yee Chia (Deputy Chief Executive (Innovation & Enterprise), A*STAR) "Accelerating Electronic-Photonic System Design and Integration - Regional Innovation Meets Global Needs" |
| 10:20 | 10:40 | Coffee Break |
| 10:40 | 11:20 | Keynote: Mr. Kengeri, Subramani (Corporate Vice President and GM, Systems to Materials, Applied Materials) "System Technology Co-optimization in AI System Solutions" |
| 11:20 | 12:00 | Keynote: Prof. Yeo, Seng Kiat (Singapore University of Technology and Design) "The Rise of AI and Its Impact on ICs" |
| 12:00 | 12:40 | Lunch Break |
| 12:40 | 13:20 | Keynote: Mr. Chan, Don (Vice president, Research & Development, Cadence Design Systems, Inc.) "From Point Tools to Agentic AI: How EDA has impacted the Semiconductor Industry" |
| Start | End | Orchid 4301 | Orchid 4302 | Orchid 4303 | Orchid 4304 | Orchid 4201 | Orchid 4202 | Orchid 4203 | Orchid 4204 |
|---|---|---|---|---|---|---|---|---|---|
| Workshop “Bridging the gaps: virtual fabrication for DTCO/STCO”-I | Panel Session 01: Digital Twins for Verification & Manufacturing: Closing the Loop From Model to Fab | Special Session/EDA Standards | Heterogeneous & Optical Compute-Infrastructure Innovations | Logic and High-level Synthesis | Fast Thermal & Reliability Modeling for 3D ICs | Hardware Design, Verification & ML-Enabled RTL | Invited ONLY | ||
| 13:30 | 13:50 | [Invited: Shen, Chen] Virtual Fabrication Platform for DTCO/STCO |
[Invited: Brophy, Dennis] EDA at Inflection Points: The Critical Role of Open Standards from Languages to Agentic AI |
[Paper ID: 109] Differentiable Timing-Aware Tier Partitioning with Hypergraph Extension for Heterogeneous 3D ICs |
[Paper ID: 40] A Novel Iterative Pairing Selection (IPS) Framework for FPGA Dual-Output LUT |
[Invited: Yu, Han] Highlights to Full Flow 2.5/3D Chiplets Toolsuit and Development Trend |
[Paper ID: 77] Pella: A Coq-based Hardware Description Language Infrastructure |
||
| 13:50 | 14:10 | [Invited: Fong, Xuan-Yao] Devices-to-systems co-design methodologies (tentative) |
[Invited: Blaimberger, Frank L.] Trustworthiness in the future of automation – AI based decision capabilities for safety and security |
[Paper ID: 118] ELITE: Efficient Lookup Table Assisted Routing Engine for Photonic Integrated Circuits |
[Paper ID: 189] AXON: An Automated Netlist Optimization Framework for High-Speed Adders |
[Paper ID: 148] IC-MoE: Interface-Constrained MoE for Fast Thermal Evaluation in 3D ICs |
[Paper ID: 172] Prompt-Set: Bridging the Semantic and Optimization Gaps in LLM-Assisted HLS via Deep Structural Refactoring and System-Level Closure |
||
| 14:10 | 14:30 | [Invited: Wang, Zhi-Ang] Taiwei - an open-source 3D physical implementation flow | [Paper ID: 132] Accuracy-Configurable Floating-Point Multiplier Design for SRAM-Based Compute-in-Memory |
[Paper ID: 211] Timing-Oriented DFF and Splitter Refinement for RSFQ Circuits |
[Paper ID: 163] OSF: An Operator-Splitting Framework for Fast Heterogeneous Thermal Simulation |
[Paper ID: 194] Error-Constrained Cost-Driven Synthesis of General-Purpose Special Function Units |
|||
| 14:50 | 15:10 | [Invited: Liu, Bin] TBA | [Paper ID: 237] OptINC: Optical In-Network-Computing for Scalable Distributed Learning |
[Paper ID: 257] An MLIR-Based Compilation Flow for CGRAs: Optimized CDFG Generation, Control-Flow Handling, and Scalability |
[Paper ID: 224] Electromigration Stress Prediction for Power Delivery TSVs in 3D ICs Using Hierarchical Heterogeneous Graph Attention Networks |
[Paper ID: 164] Lightweight RISC-V ISA Extensions for Efficient ML-KEM and its Ascon Variant |
|||
| 15:10 | 15:30 | [Invited: Wang, Xu-Peng] Process-in-memory technology with new material and devices (tentative) | [Paper ID: 150] CoPU-RL: A Hardware-Friendly Training-Inference Framework For Implementing Neuro-Symbolic Reinforcement Learning |
||||||
| 15:30 | 16:00 | Coffee Break | |||||||
| Workshop “Bridging the gaps: virtual fabrication for DTCO/STCO”-II | Topology/Layout, ADC & LLM-enabled Synthesis | Special Session/EDA Standards | Formal Verification & Equivalence Checking | Timing Analysis & Optimization | Lithography & Mask Optimization | Placement & Floorplanning Algorithms | Panel Session 02: Agentic AI + Scalable Compute in EDA: From Point Tools to Flow Orchestration | ||
| 16:00 | 16:20 | [Paper ID: 115] A Novel CNN-Based Design Framework for Incorporating Electrical Chip-Package Interaction with Application to Bandgap Reference Design |
[Paper ID: 100] CondEC: Equivalence Checking under Conditions |
[Paper ID: 22] Sparse-GCS: A High-Performance GPU Timer for Composite Current Source Model-Based STA |
[Paper ID: 13] U-WNO-ILT: U-Net Enhanced Wavelet Neural Operator with Spectral-Spatial Decoupling for Inverse Lithography |
[Paper ID: 4] ILSDP: An Iterated Local Search Algorithm for Routing-Aware FPGA Detailed Placement |
|||
| 16:20 | 16:40 | [Paper ID: 157] Automated Synthesis of Abuttable Macros for Analog Layout |
[Paper ID: 110] Symbolic Method for Static CDC Checking |
[Paper ID: 52] GraphDTA: Fast Dynamic Timing Analysis for Circuits with Graph Representation Learning |
[Paper ID: 20] TC-FNO: Fourier Neural Operator with Learnable Time-Step Embedding for 3D Lithography Exposure Simulation |
[Paper ID: 107] SWIFT-Place: Sequential Wirelength, Interposer Footprint, and Thermal-Aware Placement for 2.5D Advanced Packaging Systems |
|||
| 16:40 | 17:00 | [Paper ID: 177] SpecMind: Automated Analog-to-Digital Converter (ADC) Diagnosis with Agentic Reasoning |
[Paper ID: 178] A Phase-Coordinated Optimization Framework for Accelerating SAT-Sweeping |
[Paper ID: 59] Pre-routing Timing Prediction with Global Netlist Topology Awareness |
[Paper ID: 18] Adaptive Frequency-Domain Optimization for Lithography Mask Synthesis with Topological Constraints |
[Paper ID: 160] Reinforcement Learning-based 3D Floorplanner with Die Swapping Mechanism |
|||
| 17:00 | 17:20 | [Paper ID: 214] A Hardware-Efficient Adaptive Two-Stage Digital Calibration Method for SAR-Assisted Hybrid ADCs |
[Paper ID: 228] Efficient SAT Sweeping via Direct Circuit-Based SAT Solving |
[Paper ID: 156] ElmoreCeff: An Elmore-like Delay Calculator based on a Closed-Form Effective Capacitance Model for GPU-Accelerated Timing-Driven Optimization |
[Paper ID: 57] Efficient Mask Optimization via Brownian Bridge Diffusion Model |
[Paper ID: 179] Macro Placement Algorithm Based on Monte Carlo Tree Search and Bayesian Optimization |
|||
| 17:20 | 17:40 | [Paper ID: 199] Causally-Grounded Generation: LLM-Based Analog Circuit Synthesis via Causal Hierarchy |
[Paper ID: 242] AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking |
[Paper ID: 233] Fast Timing Analysis Framework Considering Manufacturing and In-field Operation for Silicon Lifecycle Management |
[Paper ID: 215] MODiff: Layout-Guided Mask Optimization via Diffusion Model |
[Paper ID: 180] ESPlace: Fast Macro Placement Using Evolution Strategy with Partial Evaluation |
|||
| 17:40 | 18:00 | [Paper ID: 204] TopoSynth: Explainable and Sample-Efficient Topology Synthesis of Analog/Mixed-Signal Circuits via an LLM-powered Multi-Agent System |
[Paper ID: 193] Orion: Automated Verification of Randomized Dynamic Schedules for Dataflow HLS |
[Paper ID: 270] Gradient-Guided Hierarchical Lagrangian Optimization for Timing ECO |
[Paper ID: 254] Differentiable Optical Proximity Correction for Metasurfaces Using a Pitch-Conditioned Neural Operator Surrogate |
[Paper ID: 219] Flexible Double-Side Pin Redistribution with Efficient Virtual-Net-Guided Cell Type Assignment |
|||
| Start | End | Peony Ballroom |
|---|---|---|
| 18:30 | 20:00 | Banquet/Gala Dinner |
| Start | End | Peony Ballroom |
|---|---|---|
| 08:30 | 09:10 | Keynote: Prof. Parhi, Keshab (University of Minnesota) "Energy-Efficient Domain-Specific AI Models and Agents" |
| 09:10 | 09:50 | Keynote: Prof. Chakrabarty, Krishnendu (Fulton Professor of Microelectronics, Arizona State University) "Toward Self-Healing Interconnects in Advanced Packaging: Defect Analysis, Built-in Self-Test, and Repair" |
| 09:50 | 10:30 | Keynote: Prof. Alioto, Massimo (National University of Singapore) "Advances in Energy-Efficient Always-On AI Accelerator Architectures - From Battery-Powered to Purely-Harvested Systems" |
| 10:30 | 11:00 | Coffee Break |
| 11:00 | 11:40 | Keynote: Prof. Takahashi, Atsushi (Institute of Science Tokyo) "Routing Algorithms - from the basics to recent advances" |
| 11:40 | 12:20 | Keynote: Prof. Wunderlich, Hans-Joachim (Professor Emeritus of the University Stuttgart) "From Hidden Faults to Observable Failures" |
| 12:20 | 13:30 | Lunch Break |
| Start | End | Orchid 4301 | Orchid 4302 | Orchid 4303 | Orchid 4304 | Orchid 4201 | Orchid 4202 | Orchid 4203 | Orchid 4204 |
|---|---|---|---|---|---|---|---|---|---|
| Compact Modeling & Parameter Extraction | SCIS Special Session on Advanced IC Design and Technology in AI Era | AI-Driven Front-End & Circuit Optimization | Panel Session 03: Chiplets at Scale: Can Standards, Packaging, and Qualification Enable a True Multi Vendor Ecosystem? | Routing & Layout Engines | Reliability, Device-Circuit Co-Optimization & Emerging Tech | In-Memory Computing: Architectures for AI, Security, and Beyond | Invited ONLY | ||
| 13:30 | 13:50 | [Invited: Chen, Shen] Modernization of TCAD: New Scenario & New Platform & New Solver |
[Invited: Yang, Jun] Evaluation of LLM in IC Design |
[Paper ID: 53] Discriminative Joint Representation Learning via High-Fidelity Point Clouds for Pattern Clustering |
[Paper ID: 61] GeoTrans: A Geometry-Driven Transitive Connectivity Resolution Engine for Efficient Layout Net Tracing |
[Paper ID: 9] GNN-reliability: A function-aware graph neural network for reliability prediction of gate-level netlist |
[Paper ID: 17] BioAP: A Bidirectional Digital-Slope ADC–Based In-Memory Architecture for Output-Aware Point Cloud Feature Computation |
||
| 13:50 | 14:10 | [Invited: Liu, Wenchao] DTCO: Synergizing Design and Manufacturing, Building Application-Driven EDA Flows |
[Invited: Chang, Chip-Hong] Silicon Last Stand: Security in the Artificial Intelligence of Everything (AIoE) Era |
[Paper ID: 72] LEGO: An LLM Skill-Based Front-End Design Generation Platform |
[Paper ID: 83] SNTRoute: Scalable Negotiation-Based Transistor Routing with Dense-Grid Exploration for Standard Cell Layout Synthesis |
[Paper ID: 146] Graph Neural Network-based Prediction of SEU-type Sensitive Registers in Gate-level VLSI Circuits |
[Paper ID: 37] Tackling KV-Cache Stress with Heterogeneous Dynamic LLM Inference |
||
| 14:10 | 14:30 | [Paper ID: 74] PINN-2DFET: A Physics-Informed Neural Network for Compact Modeling of 2D FETs |
[Invited: Xu, Qiang] Architecting for Jagged Intelligence |
[Paper ID: 113] GT-Fusion: Synergizing LLM Semantics, Topology, and Geometry for PPA Prediction and Optimization |
[Paper ID: 97] Unified Sequence Modeling for Joint PCB Placement and Routing via Causal Transformers |
[Paper ID: 188] Physics-Informed and Uncertainty-Aware Surrogate Modeling of Single-Event Transients for Aerospace Applications |
[Paper ID: 44] Triple-Encrypted Stochastic Computing-in-Memory Architecture for Secure CNN Inference |
||
| 14:30 | 14:50 | [Paper ID: 95] A Sensitivity-Guided Progressive Layered Extraction Neural Network for BSIM-CMG Parameter Extraction |
[Invited: Wu, Heng] Extending Moore's Law from Wafer Backside: from Interconnect to Device Integrations |
[Paper ID: 135] OpenOpt: An Open-Source SRAM Optimizer Based on Equivalent Circuit Model |
[Paper ID: 143] Preventing Clock Routing Short with Noisy Label Correction under Worst IR Drop Constraints before Power Planning and Placement |
[Paper ID: 264] On the Understanding and modelling of Negative Bias Temperature Instability (NBTI) under AC conditions |
[Paper ID: 133] CoCIM: A Collaborative Design Framework for Multi-Network Shared Compute-in-Memory Architectures |
||
| 14:50 | 15:10 | [Paper ID: 171] AgenticPE: A Dual-Agent LLM Framework with Physics-Gated Reasoning and Trajectory-Aware Optimization for Model Parameter Extraction |
[Paper ID: 155] CircuitMind: Achieving Human-Level Circuit Efficiency via Multi-Agent Collaboration and Gate-Aware Benchmarking |
[Paper ID: 251] RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System |
[Paper ID: 93] Reliability-aware DTCO with Physics-Constrained Machine Learning Framework for MOSFETs Trap Extraction |
[Paper ID: 169] A MRAM TCAM with Static Match-Line and Search Line Gating for Low-Power and High-Speed Search |
|||
| 15:10 | 15:30 | [Paper ID: 182] A Physics-Based OTS Compact Model with Force-Driven Adaptive Damping and Differentiable Hysteresis |
[Paper ID: 176] Magic Gourd: An AI Agent for Interactive Chip Front-End Design |
[Paper ID: 269] Delayed Exposure of Clock Routing Short Risk Across Technology Nodes Under PDN Configuration Variations |
[Paper ID: 197] Toward Aging-Aware Silicon Lifecycle Management in Advanced Technology: In-Situ Monitor Design, Deployment and AVS Architecture |
[Paper ID: 244] NICE: 3D-NAND-based In-Memory-Computing with In-Situ ECC-Protection for Fault-Tolerant and Efficient LLM Inference |
|||
| 15:30 | 15:50 | [Paper ID: 232] Fast Generation Strategies for cell library characterization in Advanced Technology Node |
[Paper ID: 227] RTLPilot: Skill-Driven Multi-Agent System for Repository-Level RTL Code Migration |
[Paper ID: 168] H-COSY: Hardware-Calibrated Co Optimization for Device-Circuit Synergy in Ferroelectric SNNs |
[Paper ID: 258] Toward Reliable Analog In-Memory Computing: Co-Design of Hardware-Aware Input Processing and Accuracy-Optimized Weight Mapping |
||||
| 15:50 | 16:10 | [Paper ID: 234] IBISgen: An Agent-based Framework for Automated IBIS Model Generation |
[Paper ID: 206] Enabling High-Performance VGAAFET SRAM through Gate-Via Placement and Coupling Interconnect Co-Optimization |
||||||
| 16:10 | 16:30 | [Paper ID: 220] Gradient-Driven Yield Optimization for Carbon Nanotube Circuits |
| Start | End | Out of Conference Venue |
|---|---|---|
| 16:50 | - | Excursion |
| Start | End | Peony Ballroom |
|---|---|---|
| 09:00 | 09:40 | Keynote: Prof. Gupta, Puneet (University of California, Los Angeles) "Scale-out Chiplet Based Systems: Design, Architecture and Pathfinding" |
| 09:40 | 10:00 | Morning Coffee Break |
| 12:00 | 13:30 | Lunch Break |
| Start | End | Orchid 4301 | Orchid 4302 | Orchid 4303 | Orchid 4304 | Orchid 4201 | Orchid 4202 | Orchid 4203 | Orchid 4204 |
|---|---|---|---|---|---|---|---|---|---|
| Device Characterization, Cryogenics & Cross-Layer Design | Automated Circuit Design & Optimization | Prediction & Netlist Analytics | Test, Emulation, Layout & Lifecycle Tools | Power, IR Drop & Waveform Prediction (ML-Accelerated) | Layout, Pattern Matching & Front-End Cell/Mask Flow | Architecture, Placement, Routing & Security | Invited ONLY | ||
| 10:00 | 10:20 | [Paper ID: 70] Compact Modeling and Characterization Strategies for CMOS Technology Down to 9 mK: From Physics to Simulation |
[Paper ID: 26] TopMat: Knowledge Transfer and Hierarchical Optimization for Analog Circuit Sizing via Sub-circuit Topology Matching |
[Paper ID: 108] GSGNN: A novel GSegment-based Graph Neural Network for VLSI Pre-Routing Congestion Prediction |
[Invited: Yang, Wu] Industrial trends for silicon lifecycle management |
[Paper ID: 27] PowerCube: A Formula-in-the-Loop Framework for Cross-Stage Power Map Prediction |
[Paper ID: 73] Layout Pattern Matching Using Edge-Vector Sparse Sequences and Dual-Anchor Probing |
[Invited: Zhao, Yi] 2.5D/3D Advanced Packaging EDA⁺STCO New Paradigm: architecting & physical implementation, simulation, and testing |
|
| 10:20 | 10:40 | [Paper ID: 104] Tail-Aware Variability Simulation for Planar CMOS under Cryogenic Condition: From Compact Modeling to SPICE Integration |
[Paper ID: 138] MEMO: Dynamic Routing Mixture-of-Experts Reinforcement Learning for Multi-Objective Analog Circuit Sizing |
[Paper ID: 203] ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction |
[Invited: Huang, Zheng] Addressing DFT Challenges in Advanced Packaging: Implementation and Application of EDA Solutions |
[Paper ID: 36] Aging Aware Adaptive Voltage Scaling for Reliable and Efficient AI Accelerators |
[Paper ID: 127] CAPCell: Standard Cell Layout Synthesis with Parasitic Capacitance Aware Parallel Sampling |
[Paper ID: 79] Fast, Feasible Chiplet Placements via Warm-Start Multi-Objective Reinforcement Learning |
|
| 10:40 | 11:00 | [Paper ID: 126] First Demonstration of Cell Level Electro-Thermal Coupled Full TCAD Simulation Based on Quantum Transport Framework |
[Paper ID: 174] Portable Expertise for Analog Sizing: A Data-Agnostic Foundation Model Approach |
[Paper ID: 249] LSnce: Large-Scale Netlist Constraint Extraction via Graph Similarity Learning |
[Paper ID: 33] Reducing SQED Duplicate Mode via Processor-Level Abstraction |
[Paper ID: 170] Highly Accurate Power Estimation in FPGA HLS via Adaptive and Enhanced Subgraph Learning |
[Paper ID: 162] DTCO Dual-Sided Standard Cells with DP-Based Optimization and Custom Library Development |
[Paper ID: 263] RouteFlow: A Routing-Efficient CGRA Framework Through Accelerated Layout-Aware Mapping |
|
| 11:00 | 11:20 | [Paper ID: 103] KAN-CHAR: Efficient Cell Library Characterization for DTCO via Kolmogorov-Arnold Graph Learning |
[Paper ID: 241] PARADIGM: Pareto-Optimized Analog Design via Intelligent Database-Guided Methodology |
[Paper ID: 273] AccUnit: Accelerating Unit Level Verification for RISC-V Processors Using FPGA |
[Paper ID: 65] AgentFA: The first Agent-assisted Failure Analysis framework for DRAM Test Efficiency Improvement |
[Paper ID: 218] MiniViT: A Lightweight and Physics-Aware Vision Transformer for Efficient IR Drop Prediction in Multi-Layer PCBs |
[Paper ID: 175] Lithography Test Layout Generation Using DRC-Constrained Large Language Models |
[Paper ID: 136] GNN-Accelerated Magnitude Vector Fitting Method for Rapid Pole Identification and Transient Simulation of 2.5D Power Delivery Networks |
|
| 11:20 | 11:40 | [Paper ID: 117] High-Density NAND-Like In-Plane SOT-MRAM with Robust and Efficient Write Scheme |
[Paper ID: 261] SP-BO: Simulation-Pruning Bayesian Optimization via Conformal Filtering for Efficient Analog Sizing |
[Paper ID: 120] Automated SVA Generation with LLMs |
[Paper ID: 243] SpecWave: Spectral-Enhanced Graph Learning for Crosstalk-Aware Waveform Prediction |
[Paper ID: 226] Area-Efficient Synthesis of ESD Local Clamps via Floorplan-Aware Optimization and Conduction-Duration Constrained Sizing |
[Paper ID: 195] Reuse, Reduce, Compute: A Similarity-Aware Accelerator for Diffusion Model Inference |
||
| 11:40 | 12:00 | [Paper ID: 239] Parasitic-aware SRAM Designs with 2nm Predictive Technology incorporating Baskside Contact |
[Paper ID: 165] GRIND: GNN and Reinforcement Learning Enhanced Multilevel Nested Dissection for Circuit Matrix Reordering |
[Paper ID: 166] MFchip: A Multi-FPGA Emulation Platform for Chiplet-Based Systems with Latency and Bandwidth Adaptation |
[Paper ID: 267] HeteroPower: A CPU-GPU Heterogeneous Engine to Accelerate Gate-Level Power Analysis |
[Paper ID: 134] Anti-AdvTamp: Exposing Adversarial Evasive Tampering Attacks in Network-on-Chips with a Multi-Scale Attribute Fusion Detection |
|||
| 12:00 | 12:20 | [Paper ID: 260] A Cross-Layer Inverse Design Framework from Device to Circuit Using Artificial Neural Networks and Pareto Optimization |
[Paper ID: 259] Efficient and Scalable Parallel Net Tracing for Large-Scale Industrial Layouts via Hybrid Spatial Indexing |
||||||
| 12:20 | 13:30 | ||||||||
| 13:30 | 16:30 | [Tutorial 01] Parallel Sparse Direct Solver for SPICE |
[Tutorial 02] ECOS Studio: Building an Open Ecosystem for Silicon Design and Education |
[Tutorial 03] AI for EDA Feedback Loops: Leveraging Manufacturing Data to Evolve PDKs, Models, and Design Rules |
[Tutorial 04] CMOS Technology and Its Application to Design Multi-Standard RF/mm-Wave Low-Noise Amplifiers |
[Tutorial 05] Design methodologies for intelligent & perceptive hardware security - From circuits to machine learning algorithms |
[Tutorial 06] Design of Energy-Constrained AI Accelerators for Edge Computing |
[Tutorial 07] Sub-THz Circuits and Systems for Radar Transceivers |
| Start | End | Peony Ballroom |
|---|---|---|
| 14:00 | 18:30 | Summer of Talent |