Deep Learning Inspired Capacitance Extraction for IC Interconnects
Invited Speaker: Wenjian Yu, Tsinghua University
Abstract: In this talk, I’ll review the research progress on IC capacitance extraction, especially the usage of deep-learning technologies in the relevant problems. Firstly, a method based on GNN for predicting the capacitance parasitics in the pre-layout design stage is presented. It exhibits potential benefit for the design optimization of some specific circuits like SRAM. Then, the deep-learning-inspired methods for post-layout capacitance extraction are presented. They can revamp the accuracy drawback of layout parasitic extraction (LPE) method and efficiency drawback of 3-D capacitance field solver. These methods include CNN-Cap, GNN-Cap and NAS-Cap. Lastly, I’ll briefly review the progress on the random walk based 3-D capacitance solver, especially the deep-learning-aided technique for improving its accuracy for the structures under the advanced process technology.
PCT-Cap: Point Cloud Transformer for Accurate 3D Capacitance Extraction
Presenter: Yuyao Liang, Shenzhen University
Abstract: Accurate parasitic capacitance extraction becomes increasingly essential in advanced technology nodes. 2.5D extraction requires more effort to maintain accuracy comparable to the 3D solver. In this work, two experiments reveal that error deviation in the 2.5D method enlarges as wire width shrinks and length increases. A novel Gauss law-based point cloud is proposed to model the 3D capacitance problem. With the proposed data representation, a transformer-based neural network architecture, called PCT-Cap, is designed for 3D pattern matching. PCT-Cap exhibits much better performance than the ResNet-based capacitance models. Extensive experiments on 28nm technology demonstrate that PCT-Cap can accurately predict over 95.41% of total capacitance with an error margin of less than 5%. Additionally, PCT-Cap achieves 95.90% accuracy in predicting coupling capacitance within a margin of error of less than 10%. PCT-Cap achieves at least a 55 times speeding up compared with the commercial extraction tool while consuming negligible memory.
Fast Electromigration Stress Evolution Analysis Based on Relative Gain Array
Presenter: Wenjie Zhu, Shanghai Jiao Tong University
Abstract: As technology moves to smaller feature sizes and interconnect current densities continue to increase, electromigration (EM) poses a significant challenge to the reliability of the large integrated circuit design. In order to improve the efficiency of the EM stress analysis for any general interconnect or power grid, we introduce an efficient electromigration analysis approach based on decentralized model order reduction (MOR). Initially, the original Multi-Input Multi-Output (MIMO) system obtained by discretization is decoupled into a series of Multi-Input Single-Output (MISO) subsystems through the application of the Relative Gain Array (RGA) matrix. Subsequently, each subsystem is reduced by MOR techniques, thereby obtaining the reduced low-order subsystem corresponding to the certain output port for EM stress evolution analysis. By conducting simulations and numerical calculations on the resulting subsystem, the calculation efficiency can be greatly accelerated while maintaining the accuracy of EM transient analysis. Experiments demonstrate about 11X-187X speedup over COMSOL and about 11X-32X speedup over the standard transient analysis of original system, while the error is almost negligible.
UCMNet: Static IR Drop Estimation Using Attention Convolutional Network
Presenter: Jitao Yu, Southeast University
Abstract: In the current chip design flow at advanced process nodes,IR drop analysis is a critical step in chip signoff, which requires expensive computation and a long time. In this work, we propose a machine learning (ML) model based on improved convolutional neural networks (CNN). It takes multiple maps of the full-chip design and features of instances as input, enabling rapid and accurate estimation of instance-level static IR drop. Experimental results show that the model achieves 330X speedup compared to existing commercial tools, with high average CC values (0.9737) and low average MAE values (0.6833mv). Furthermore, compared to existing ML methods the maximum improvement in accuracy can reach 87.2%.
UnetPro: Combining Attention with Skip Connection in Unet for Efficient IR Drop Prediction
Presenter: Zhengfei Qi, China University of Petroleum
Abstract: IR drop analysis plays a key role in chip design. Unlike conventional time-consuming numerical analysis methods, which involve solving large-scale linear circuit equations, predicting the IR drop with machine learning shows great potential to significantly reduce computation time. However, applying machine learning for accurate prediction is non-trivial since achieving effective feature extraction poses significant challenges. Furthermore, as the number of layers in the neural network model increases, the loss of information in the transmission process gradually increases, leading to inaccurate prediction results. In this paper, we propose UnetPro, an innovative machine learning model to resolve these challenges. We leverage an attention mechanism that combines both global and local information and a multi-scale convolution module to make the model sufficiently perceive the various regions of the feature map, enhancing the feature extraction ability of the model. Moreover, we ensure the coherence of information by introducing skip connection. We also introduce the dropout mechanism to ensure the stability of model with information transfer. Compared with conventional Unet model, the error and correlation of our proposed algorithm are lower than it by 2.5e-4 and higher by 10.34\%, respectively.
Deep Learning Inspired Capacitance Extraction for IC Interconnects
Invited Speaker: Wenjian Yu, Tsinghua University