Design Automation of Analog Circuits

Abstract: Manual design processes are time-consuming and often rely heavily on designers' experiences. Design automation offers a solution by leveraging algorithms and tools to streamline the design process, optimize performance, and reduce the time-to-market. In this tutorial, we will cover the TED system, transistor sizing and physical design algorithms for analog circuits. The tutorial is scheduled as follows.

Agile Design Tools for In-Memory Computing Systems: from Macro Circuit to Architecture

Abstract: In-memory computing (IMC) or processing-in-memory (PIM) is an emerging technology for non-Von-Neumman architecutre, where computations are performed directly within the memory itself, rather than being sent to a separate central processing unit (CPU). Thanks to the tight coupling between computing logics and memory designs, IMC’s latency and power consumption are much better than traditional architecture. In addtion, leveraging either analog circuit or custim digital gates, IMC also features good energy efficiency. From an Electronic Design Automation (EDA) perspective, however there lacks mature tools to complete a IMC system as agile as traditional digital design. The tutorial provides an overview of the latest advancements in agile compute in memory tools , from macro to architecture level.
The first half of the turial covers an overall introduction for the IMC macro compiler, namely automatic synthesis and physical design tools for IMC macros. A circuit generator and agile placement-and-routing tool for both analog and digital IMC macros is first demonstrated. In addtion, an improved version of robust IMC complier with MBIST is discussed, which supports configuration of integer and floating point modes.
The second half will introduce several architectural level tools for IMS system design. It includes an automatic architecture synthesis tool for generating NVM crossbar-based DNN accelerators, a universal compilation framework for PIM DNN accelerators, and a full-system PIM simulator to facilitate circuit-, architecture- and system-level researches.

Boolean Satisfiability Solving, State-of-the-Art

Abstract: The Boolean satisfiability (SAT) problem, a fundamental issue in computer science, revolves around determining the existence of an interpretation that satisfies a given Boolean formula, typically represented in conjunctive normal form (CNF). It holds the distinction of being the first problem proven to be NP-complete, highlighting its significance in computational complexity theory.
The realm of SAT solvers has witnessed remarkable growth, with numerous techniques developed and applied across various domains. In fields such as electronic design automation (EDA), SAT-based methodologies play a pivotal role in logic reasoning tasks such as equivalence checking, SAT sweeping, and automatic test pattern generation (ATPG). Conversely, EDA techniques can be harnessed to enhance SAT-solving efficiency through avenues such as circuit-based SAT solvers, logic synthesis, and AI-driven approaches.
In this tutorial, we have planned three talks to address different aspects of SAT problem-solving. Our first session will provide an in-depth exploration of SAT fundamentals and elucidate recent advancements in solving techniques. Following this, our second talk will spotlight the synergy between logic synthesis and AI-driven methodologies in boosting SAT-solving capabilities. Finally, our third session will introduce a novel reasoning engine based on semi-tensor product and circuit-based SAT solvers, offering a fresh perspective on tackling SAT problems.

Benchmark for 2023 Integrated Circuit EDA Elite Challenge

Abstract: This tutorial focuses on the benchmarks of the four competition problems from the 2023 Integrated Circuit EDA (Electronic Design Automation) Elite Challenge. It emphasizes the design philosophy, application scope, and usage process of these benchmarks. The expectation is that through this tutorial, more scholars and students can be assisted, thereby promoting research and exploration in the related fields.

Enabling Large Language Models in EDA

Abstract: In this tutorial, we aim to showcase the transformative potential of large language models (LLMs) within the field of Electronic Design Automation (EDA). This session will explore a range of pioneering research efforts that leverage LLMs to address various EDA challenges, including "ChatEDA: A Large Language Model Powered Autonomous Agent for EDA," which introduces an LLM-powered tool for automating EDA tasks; "BetterV: Controlled Verilog Generation with Discriminative Guidance," focusing on generating more accurate Verilog code through LLMs; "SoLA: Solver-Layer Adaption of LLM for Better Logic Reasoning," which enhances LLMs' capability for logical reasoning in EDA applications. Participants will gain insights into the latest advancements in LLM applications for improving design automation, verification processes, and debugging efficiency, setting a new benchmark for innovation in EDA.

iEDA: An Open-source Physical Design EDA Infrastructure and Toolchain

Abstract: By harnessing the capabilities of open-source software, the EDA tool provides an economical and adaptable solution suitable for designers, researchers, and enthusiasts alike. Open-source EDA fosters collaboration, innovation, and the exchange of knowledge within the EDA community. It underscores the pivotal role of the toolchain in expediting the development of electronic systems, while concurrently mitigating design expenses and enhancing design excellence. This tutorial centers on an open-source EDA infrastructure, iEDA, which is designed to establish a fundamental infrastructure for the evolution of EDA technology and bridge the gap between industry and academia in the EDA domain. To showcase the efficacy of iEDA, we have successfully fabricated and validated four chips of varying scales (ranging from 700k to 500M gates) using different process nodes (110nm and 28nm) with iEDA. iEDA is publicly accessible via the project's homepage at https://github.com/OSCC-Project/iEDA.

Introducing Building Blocks of DTCO from GWX Technology

Abstract: For EDA vendors, DTCO (Design-Technology Co-Optimization) process enables wafer fabs and chip design companies to maintain close cooperation, reducing the development and usage risks of new semiconductor processes. OPC and Standard Cell Characterization are important building blocks in such flow. In LFD （Litho-Friendly Design）process, lithography hotspot pattern library is created at early-stage process nodes, which are then refined using previous models, machine learning, and OPC verification for accuracy. In practical design, pattern matching algorithms are employed to identify and correct hotspots within the design layouts (Hot-Spot Aware P&R). The established hotspot pattern library can be validated and optimized with real manufacturing data, ensuring its effectiveness for improved chip yield and manufacturability. Advanced device structures (such as FinFETs and GAA) cause self-heating issues, which further lead to problems with chip reliability (degradation). At the same time, chip design must ensure a zero-defect rate after manufacture and a longer operational lifespan, presenting significant challenges to chip design.
In this tutorial, GWX Library Characterization team introduces a highly accurate and efficient aging-aware stress analysis flow for CMOS circuits, incorporating a novel logical-resolving method and a machine learning-driven reliability analysis that significantly enhances STA efficiency and accuracy, guiding early-stage circuit design towards greater reliability. GWX Litho-team demonstrates a complete OPC flow and explains the concept of LFD in such process.
SMiXS team offers comprehensive chip design, verification, and mass production services, along with system-level package solutions and strategic partnerships, to enhance competitiveness and meet both Moore's Law and More-than-Moore demands, demonstrating success through advanced wafer processes and strong customer and supplier relationships.

Chip Verification Solution Based on Formal Verification

By GWX

Abstract: Verification technology plays a pivotal role in ensuring the correctness of integrated circuit. Formal verification constitutes an integral component of verification technology.With the advanced technology development, formal verification is also experiencing growth and refinement. This presentation will conduct an in-depth exploration of multiple significant aspects of formal verification technology, including the development status of chip verification techniques, an introduction to formal verification methodologies, C/RTL-to-RTL equivalence checking,RTL/Netlist-to-Netlist equivalence checking, and model checking.

Practical Training: Application of Chip Verification Solutions

By S2C

Abstract: This training course aims to provide an in-depth understanding of the core functionalities of S2C's digital EDA products and to analyze in detail the key challenges encountered in the chip design process and the corresponding strategies provided by EDA tools.
The course will use the "XiangShan" project from BOSC as an illustrative example, enabling participants to develop a systematic understanding of IC design verification processes and acquire comprehensive knowledge of prototyping analysis and practical skills. Additionally, the training will emphasize key points and practical challenges that are encountered during actual operations, helping participants establish a close connection between theoretical learning and practical application, effectively enhancing their practical abilities.

Training and Demonstration of EDA Tools for the Full Process of RF Circuit Design

By Empyrean Technology Co., Ltd

Abstract: This training is based on Empyrean's full process EDA tool for RF circuit design. It provides a detailed introduction to Empyrean Technology and its full process products, helping everyone understand Empyrean's tools and design process. This includes RF model extraction tool, RF circuit schematic editing tool, RF circuit layout editing tool, RF circuit simulation tool, RF circuit physical verification tool, etc., providing users with a complete solution from circuit to layout, from design to simulation verification.

Design Enablement Solution for Novel Semiconductor Devices Research

By Primarius

Abstract: The advancement in semiconductor research has led to the development of novel devices and materials with superior performance. Integrating these innovations into existing chip design flow is essential, requiring the creation of SPICE models, Process Design Kits (PDKs).
The development of SPICE models and PDKs for novel devices places high demands on the flexibility and scalability of EDA tool. Primarius’s EDA products address these requirements comprehensively, offering robust support for these tasks.
This tutorial, “Design Enablement Solution for Novel Semiconductor Devices Research,” focuses on novel semiconductor devices such as wide bandgap semiconductors (SiC, GaN etc.), Thin-Film Transistors (TFT), and superconducting Josephson junctions. It offers unique hands-on experimental opportunities for participants to directly engage with these technologies using Primarius’s tools.
This session will enable attendees to understand and apply the methodologies necessary for incorporating high-performance novel devices into mainstream chip designs. Join us to explore essential techniques in novel devices design enablement and transition pioneering research into practical applications.