EDA² | ISEDA 2024

Session Details

Technical Session 11

Co-Optimizing Systems, Design, and Technology

Session Chair: Xingsheng Wang, Huazhong University of Science and Technology

New AI Approach of Foundry-based DTCO Methodology for Next-Generation EDA Applications

Invited Speaker: Gordon Shou, ICPSROOT

Abstract: EDA plays a crucial role in the semiconductor industry by enabling the creation of semiconductor chips through virtual simulation of silicon wafers. To bridge the gap between virtual design and actual manufacturing, foundry process engineers leverage device-driven EDA tools like TCAD to simulate semiconductor manufacturing processes and device operations. On the other hand, design-driven EDA tools such as the Spice model translate silicon behavior into electrical parameters for chip designers to simulate. However, a gap often exists between virtual simulation results and actual silicon wafers.
One innovative approach to address this gap is to utilize AI to build virtual manufacturing models, which leverage big data from both manufacturing process characteristics and design electrical properties. ICSprout, the world's only university-operated 12-inch wafer fab, has amassed a substantial amount of silicon data since its inception in 2022. This data, encompassing CMOS, eFlash, BCD, and other technologies, has facilitated the development of an AI virtual manufacturing model for individual process steps such as CESL, Thin Film Deposition, Oxidation, and CMP.
This paper presents the progress of an AI model for a single process step, CESL. Using approximately 16K sets of design and process silicon data from the ICSprout fab environment, an AI model was trained to predict process parameters based on the required electrical properties of the chip design. The developed AI model achieves highly accurate CESL process estimation with 97% accuracy. Notably, the prediction is bidirectional, enabling the model to provide precise electrical performance prediction given process combination inputs.
This model offers significant benefits to both designers and manufacturers, with the potential to reduce R&D costs and Design of Experiments (DOE) cycle time.

Fast System Technology Co-Optimization Framework for Emerging Technology Based on Graph Neural Networks

Presenter: Guangxi Fan, Shanghai Jiao Tong University

Abstract: In the rapidly evolving landscape of semiconductor technology, the advent of novel materials and sophisticated device architectures offers both opportunities and challenges for researchers. Efficient optimization of power, performance, and area (PPA) is essential in order to fully take advantages of emerging materials and new device structures. To address aforementioned issues, this paper presents a novel fast system technology co-optimization (STCO) framework for emerging flexible technologies. Simulation results demonstrate the advancement of our fast STCO framework with over 100X speedup in both TCAD simulation and cell library characterization comparing to commercial tools. For a comprehensive STCO iteration, covering TCAD simulation, modeling, cell library characterization and PPA evaluations, our framework achieves a runtime speedup between 1.9X to 14.1X depending on the scale of the evaluated circuits. The fast STCO framework incorporates a graph neural network (GNN)-based TCAD surrogate model, a unified compact model, and a GNN-based cell library characterization model. The developed STCO framework not only supports emerging technologies but can be applied to optimize the traditional silicon designs in advanced technology node.

Exploring Memory Optimization: Research on Resource Management

Invited Speaker: Hrachya Astsatryan, National Academy of Sciences of Armenia

Abstract: This research delves deep into memory optimization, focusing on innovative resource management strategies in computing environments. By exploring state-of-the-art technologies such as Remote Direct Memory Access (RDMA), Compute Express Link (CXL), and disaggregated memory architectures, we aim to unravel the intricacies surrounding memory mutualization systems. Through rigorous investigation and analysis, our study sheds light on novel approaches to enhance memory efficiency, scalability, and performance.

Automatic Standard Cell Layout Generator Integrated with Design Expertise

Presenter: Yuan Lei, Hong Kong Applied Science and Technology Research Institute

Abstract: Standard cell library plays a crucial role in the efficient and reliable design of integrated circuits, but layout design of standard cell library remains challenging in industry today due to the complex design and time-to-market constraint. In this work, an automatic standard cell layout generator integrated with design expertise is presented. Existing layout experience is extracted and utilized for device placement. Additionally, to solve the multiple constraints for standard cell routing, an expertise-driven hybrid routing algorithm is developed and illustrated. Experimental results show that proposed layout generator can produce competitive standard cell layouts with quality comparable to expert's design from industry.

Migrating Standard Cells for Multiple Drive Strengths by Routing Imitation

Presenter: Xiaohan Gao, Peking University

Abstract: Standard cells are critical primitives of modern integrated circuits. Designing standard cells requires time-consuming manual optimization. Within a standard cell library, designers resize standard cells with the same functionality for different drive strengths. Building up all the layouts of all drive strengths from scratch introduces a lot of repetitive and redundant work, especially in routing. We propose a standard cell resizing framework to migrate a layout to another drive strength by imitating the routing of the existing layout. Experimental results demonstrate that our framework is capable of synthesizing layouts with competitive performance with the manual layouts on an industrial standard cell library.