EDA² | ISEDA 2024

Pushing the Envelope in Physical Implementation

Abstract: As the modern CPU, GPU, and NPU chip's design complexity and transistor counts keep increasing, and with the relentless shrinking of semiconductor technology node to nearly 1 nanometer, the placement and routing have gradually become the two most pivotal processes in modern very-large-scale-integrated (VLSI) circuit back-end design. How to evaluate routability efficiently and accurately in advance (at the placement and global routing stages) has grown into a crucial research area in the field of artificial intelligence (AI) assisted electronic design automation (EDA). In this paper, we propose a novel U-Net variant model boosted by an Inception embedded module to predict Routing Congestion (RC) and Design Rule Checking (DRC) hotspots. Experimental results on the recently published CircuitNet dataset benchmark show that our proposed method achieves up to 5% (RC) and 20% (DRC) rate reduction in terms of Avg-NRMSE (Average Normalized Root Mean Square Error) compared to the classic architecture. Furthermore, our approach consistently outperforms the prior model on the SSIM (Structural Similarity Index Measure) metric.

Abstract: The shift left paradigm in Electronic Design Automation (EDA) presents a pathway for the creation of digital twins, facilitating the transition of subsequent physically-aware design processes into virtual environments. This shift empowers designers to establish stronger correlations and optimize their designs more effectively. However, it is crucial to identify when and how to implement this shift, especially considering the challenges in replicating subsequent behaviors accurately. Given that synthesis marks the initiation of the entire physical implementation phase, macro placement serves as the starting point for intensive automated placement, and timing signoff acts as a starting point for the engineering change order (ECO) process. We have pinpointed opportunities to introduce shift left updates to these critical stages. By incorporating a physically aware timing model into logic synthesis, we have significantly enhanced design quality in terms of timing. By preemptively considering macro-cell connections as a co-optimization target, improvements have been observed in routing length and congestion, leading to more efficient designs. Additionally, by closely coupling a fast and accurate timing estimation model with the following ECO process, faster timing closure has been achieved.

Abstract: Accurate prediction of routing congestion in the placement stage is critical in digital integrated circuit design. We propose an effective heterogeneous graph neural network named HeteroNet with an encoder-decoder structure, to predict global routing congestion from placement results. General heterogeneous graphs are constructed to flexibly represent layout objects and relations between them. We also propose efficient transfer learning technique on HeteroNet. Experimental results show that HeteroNet models achieve higher predictive performance compared to prior work. When having a network modeling one global router, the training of a new network modeling another global router can be achieved in only 17% of runtime using transfer learning, compared to training from scratch.

Abstract: DRC-based layout pattern matching is currently the mainstream method in the industry. However, as process nodes shrink and pattern complexity grows, the runtime of DRC-based layout pattern matching methods has increased significantly. The DRC method relies on weakly constrained one-dimensional rule checks, resulting in numerous potential matching regions. In addition, it is difficult to accurately describe patterns with DRC rules, which leads to a complex matching verification process. To address the above issues, we propose a novel edge pair-based approach that reduces the number of potential matching regions while speeding up the search process. Additionally, we employ a hash method for simplified and effective matching verification. Furthermore, as the hash method relies on spatial indexing, we utilize space-filling curves to accelerate index construction and reduce region query time. Experimental results show that compared to the state-of-the-art pattern matching method, our proposed approach achieves a speedup ranging from 5.6× to 17.3× with 100% accuracy.

Abstract: Aging effects such as NBTI, introduce new challenges to circuit design. As NBTI is heavily related to the workload features of the circuit, logic restructuring techniques are proposed to modify the signal probability of internal nodes in a circuit to reduce timing degradation. However, decreasing signal probability does not guarantee aging-aware timing improvement, since the new structure will lead to a different implementation with unexpected delay characteristics. Thus, selecting candidates for timing optimization presents a challenge during logic restructuring. In this work, we define the question as an anomaly detection problem. Critical paths of the netlist are represented with heterogeneous graphs to accurately capture the connectivity of complex logic gates. An HGAT-based autoencoder model is then deployed to learn and obtain valid candidates for a predefined logic restructure technique. The result shows improved runtime and result quality compared with traditional heuristic-based algorithms, confirming the efficacy of our proposed model.