EDA² | ISEDA 2024

Design, Safety and Reliability

Abstract: Recently, Hardware Trojans are gaining increasing attention due to their ability to cause damage to critical circuits through covert attack methods, which poses significant threats to electronic systems. Among the various attack methods of Hardware Trojans, those based on electromigration (EM) induced circuit aging are particularly feasible. In this paper, we investigate Hardware Trojan defense in integrated circuits based on an advanced three-dimensional physical electromigration model. By extracting characteristic structures from specific circuits, we conduct the electromigration failure analysis and propose Hardware Trojan defense strategy based on specific interconnect structures. Through these works, we demonstrate the vulnerable attacking locations of different interconnect structures and provide the guidance for electromigration based Hardware Trojans defense in IC design.

Abstract: With the rapid development of integrated circuit manufacturing processes, soft errors have emerged as a pivotal factor that influences circuit reliability. This paper endeavors to investigate the rapid estimation of the impact of the single event upset (SEU) on the logic behaviors of flip-flops in a circuit using machine learning methods. A major challenge currently faced when applying machine learning methods for SEU evaluation is the absence of publicly available circuit datasets. Therefore, this paper employs the fault injection method to acquire circuit data such as soft error sensitivity. Subsequently, it models the gatelevel netlist and integrates the netlist models with the acquired data to construct a dataset. Finally, a model based on graph attention network (GAT) is developed and we use the leaveone-out cross validation method to evaluate the performance. Compared to prior work based on GraphSAGE, the experimental results indicate that the method proposed in this paper has better predictive performance. It achieves an average absolute error of 0.08, representing a 38% improvement over the previous methods.

Abstract: This paper proposes an inside-aware-soft-error 16T (IASE16T) SRAM unit for aerospace applications to address single-event upsets (SEUs) caused by high-energy particles in space. It outperforms other soft error-aware SRAM units (SARP12T, LWS14T, SAR14T, RSP14T, S8P8N16T, EDP12T, SIS10T) by fully recovering from SEUs and exhibiting a critical charge exceeding 105fc, superior stability, and write latency time. Compared to alternatives, IASE16T demonstrates significantly improved hold static noise margin (HSNM) (by approximately 60%-138%). However, its read speed is slightly reduced due to having only one discharge path, and it incurs some area loss due to its 16T structure.

Abstract: Parallelism capability of GPUs makes accelerated RTL simulation possible by utilizing structure-level and data-level parallelism of designs. However, due to the existence of feedback loops in circuits, how to achieve data-level parallelism in a single testbench is still a great challenge. In this paper, we propose a novel CPGPU-accelerated RTL simulation framework with loop unrolling techniques to utilize data-level parallelism for RTL simulation acceleration. In the framework, designs under simulation are first processed by loop unrolling. Then the processed designs are partitioned and the simulation task of each partition is assigned to be simulated on CPU or GPU according to its characteristics. The design partitioning method makes full use of the parallel capabilities of RTL simulation using GPU. The promising experimental results show that the proposed CPGPU-accelerated RTL simulation achieves up to 32.2x speed-up than ESSENT and 4.8x speed-up than traditional GPU-based acceleration methods.

Abstract: Static IR drop analysis is a crucial part in the signoff stage of the IC design flow. Conventional commercial tools are often time-consuming, hindering the acceleration of the industrial design cycle. We propose a novel OhmNet neural network architecture to provide quick and accurate predictions for the limited IR drop mitigation time budget in the IC design period. OhmNet incorporates circuit constraint into the model optimization process. This approach not only facilitates the convergence of the model but also enhances its interpretability. Furthermore, the implementation of the OhmNet architecture is modular. We developed four configurable modules that can be customized to meet specific accuracy or speed requirements, leading to the creation of the OhmNet-23 network. The experimental results show that the network is still sensitive to isolated, small-scale regions with high IR drop. Compared with the ground truth, the average correlation coefficient (CC) and the mean absolute error (MAE) of the estimation result are 92.92% and 2.14 mV, respectively, and the estimation speed is 28.98% faster than the method based on U-Net.