EDA² | ISEDA 2024

Synthesis Techniques: The Next Generation

Abstract: Advanced digital designs are getting more complex and challenging in the last two decades. This trend drives commercial synthesis tools to improve on many aspects. This talk will review some key features of RocSyn and its related technologies. Furthermore, reference methodology will be presented to achieve best PPA and turnaround time.

Abstract: Logic synthesis synthesize circuit structures to optimize specific targets given reasonable constraints and runtime, utilizing a set of well-defined operators. Most existing synthesis operators are designed heuristically with a general paradigm of traversing circuit cuts or sub-graphs and making local replacements, when certain transformations offer synthesis gains. These transformations are usually obtained via invoking certain synthesis engines and can be time-consuming. However, most of these computations are redundant and lead to no further replacements. The efficiency of these operators is crucial for improving runtime and optimization convergence. Therefore, we propose a general framework for efficient logic synthesis that prunes unnecessary logic transformation and gain measurements, while maintaining synthesis effectiveness. To address the diverse needs of different operators, considering factors such as model inference time, ease of deployment, and interpretability, we propose several methods tailored to specific scenarios and unify them into a general framework. The framework is validated through experiments on both public and industrial circuits. For example, the expertise based scoring method can accelerate drw by about 35% with negligible effectiveness loss, and a GNN-basedmethod achieves up to 3.1x faster runtime of mfs2.

Abstract: With the development of large-scale integrated circuits, electronic design automation~(EDA) tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend. The optimization of delay reduction is a crucial factor for ASIC technology mapping, and supergate technology proves to be an effective method for achieving this in EDA tools flow. However, we have observed that increasing the number of generated supergates can reduce delay, but this comes at the cost of an exponential increase in computation time. In this paper, we propose a parallel supergate computing method that addresses the tradeoff between time-consuming and delay optimization. The proposed method utilizes the input-constrained supergate pattern to parallelly generate the supergate candidates, and then filter the valid supergates as the results. Experiment results show the efficiency of the proposed method, for example, it can attain the improvement of 4 times speedup in computation time and 10.1 in delay reduction with 32 threads.

Abstract: Resistive random access memories (RRAMs) serve as compact non-volatile storage devices capable of storing data and performing Boolean operations. They inherently support 3-input Resistive Majority (RM\textsubscript{3}) logic operations, making them integral to in-memory computing applications. Prior methods have adapted general-purpose logic networks for RM\textsubscript{3} logic. This paper introduces RM\textsubscript{3}-inverter graphs (RM\textsubscript{3}IGs) as dedicated logic representations, employing RM\textsubscript{3} and inverters as primitives. We utilize an exact synthesis algorithm to derive optimal RM\textsubscript{3}IG implementations for 4-input Boolean functions to establish a database. Then, leveraging a logic restructuring algorithm and the database, we derive initial RM\textsubscript{3}IG structures. Furthermore, we propose a heuristic algorithm for inversion optimization within RM\textsubscript{3}IGs. Our experimental results show a reduction in the number of nodes and inverters, demonstrating a 14.0\% reduction in size and a 17.7\% reduction in level compared to previous approaches.

Abstract: As chip development enters the “post-Moore's Law era,” the core driving force behind chip design will gradually shift from enhancements in performance power and area(PPA) consumption to building autonomous chips for emerging applications. However, bridging the gap between domain-specific systems and traditional chip design complicates the process, posing challenges for iterative chip development. Logic synthesis, as a tedious and time-consuming step at the front end of the process, stands as one of the major bottlenecks in accelerating chip iterative development. To address this, we propose a topology-flattening-based automated incremental logic synthesis method. It divides projects into functional blocks, allowing for selective re-synthesis of modified parts, significantly improving iteration efficiency. Building upon this technique, we have developed an automated synthesis system capable of flexibly integrating existing open-source synthesis tools to achieve automated incremental synthesis. Experimental testing conducted on the open-source synthesis tool Yosys demonstrates that our proposed method enhances the iteration efficiency of chip design front-end, providing an effective solution for automated incremental synthesis.