Robust Wafer Classification with Imperfectly Labeled Data
Invited Speaker: Xin Li, Duke Kunshan University
Abstract: Wafer classification is a critical task for semiconductor manufacturing. Most conventional algorithms require a large-scale perfectly-labeled dataset to train accurate classifiers. In practice, it is usually difficult or even impossible to collect perfect labels without errors, and the classification accuracy in the presence of imperfectly labeled data may substantially degrade. In this presentation, we will discuss a number of novel techniques to facilitate robust wafer classification with noisy labels. These techniques can be classified into three broad categories: (1) data cleaning methods, (2) loss-function-based methods, and (3) co-teaching methods. The efficacy of robust wafer classification will be demonstrated by several industrial datasets.
An Efficient Grouping Method for Large-Scale MBIST
Presenter: Rongjie Yang, Sun Yat-sen University
Abstract: Memory built-in self-test (MBIST) is an important design-for-test (DFT) technique for embedded memories, and MBIST grouping is the most significant part of it. However, as the number of embedded memories increases, previous MBIST grouping methods result in long grouping time or low-quality grouping results. In this paper, we propose an efficient grouping method for large-scale MBIST. Our method combines greedy algorithm (GA) with simulated annealing algorithm (SA), reducing grouping time significantly while maintaining high-quality grouping results. Experimental results show that, compared to previous SA-based methods, our method can reduce grouping time by 43\% for large-scale MBIST. It reduces the number of groups by 178 and 17 for large-scale MBIST compared to previous SA-based and GA-based methods, respectively.
EMGA: An Evolutionary Memory Grouping Algorithm for MBIST
Presenter: Yang Li, China University of Petroleum
Abstract: MBIST (Memory Built-In Self-Test) is a widely used methodology in chip design and fabrication to detect and localize faults in memories. Due to the large memory sizes of modern chips, memories need to be grouped in order to manage and test them efficiently. However, due to the high number of constraints and memories, the time complexity of solving directly using heuristic algorithms is high and the grouping results obtained are of poor quality. In this paper, we propose a heuristic-based MBIST grouping algorithm to maintain high efficiency while achieving high quality grouping. We firstly divide the numerous constraints into two categories to reduce the constraint dimensions and obtain an initial grouping result. We then use a greedy algorithm with a penalty term to quickly obtain the result that satisfies all the constraints from the initial result in order to reduce the time consumption and the size of the grouping. In order to avoid local optimal solutions, we further use an improved genetic algorithm to optimize the result of the greedy algorithm to obtain higher quality groupings. The experimental results demonstrate that our algorithm reduces the number of groups 119.44% on average compared with the K-Means method. Compared with simulated annealing algorithm and genetic algorithm, EMGA reduces the number of groups by 8.35% and 4.66%, and time by 79.51% and 73.30%, respectively.
An efficient grouping algorithm with build-in-self-test for multiple memories
Presenter: Zhixing Liu, Xidian University
Abstract: With the advancement of manufacturing processes and the ever-increasing demand for system-on-chip (SoC) computations, modern SoCs integrate a myriad of embedded memories, posing significant challenges for memory unit testing. Presently, the Memory Built-in Self Test (MBIST) method is often used by industry to effectively test memories. However, the burgeoning quantity of memories entails substantial resource waste when allocating test logic for each memory unit. It is imperative that the auxiliary circuitry for testing purposes remain minimal while fulfilling the testing requisites. Rational grouping of memories to share Built-In Self-Test (BIST) logic to mitigate unnecessary overhead during testing emerges as a plausible research problem. In this paper, we propose an efficient three-step partitioning approach for shared memory BIST logic, focusing on grouping rules and variable constraints. This methodology is applicable to diverse memory types and BIST components. With the objective of minimizing the number of memory groups while satisfying constraints, our approach aims to reduce BIST logic, thereby mitigating area overhead. Following the initial partitioning to generate compatible memory groups, a multi-threaded approach is employed for the subsequent partitioning of all memory groups. By representing memories that satisfy distance constraints as graphs and substituting the greedy algorithm with the BronKerBosh algorithm, superior solutions are attained. Experimental results indicate an average improvement of 9% in solution quality compared to the greedy algorithm.
An Efficient SRAM Yield Analysis Method using Multi-Fidelity Neural Network
Presenter: Zhongxi Guo, Southeast University
Abstract: As microelectronic fabrication technology advances rapidly, the yield of static random access memory (SRAM) blocks has to be guaranteed at a high level due to the large number of replicated cells. Accurate and efficient yield analysis methods are in great demand to reduce manufacturing costs induced by process variations. In this article, we integrate multi-fidelity (MF) neural networks as surrogate models into the importance sampling (IS) method, which expedites the search process for optimal shift vectors (OSV). Compared to the conventional OSV searching methods, the proposed method significantly reduces the number of simulations required for model training while maintaining accuracy. Finally, the failure rates are estimated using IS process until convergence. The experimental results on the 64-bit SRAM column show that preserves the advantages of IS-based methods, achieving up to 2.1$\times$ to 14.3$\times$ the efficiency and accuracy compared to the state-of-the-art methods for high-dimensional circuits.
RLIF-Net: Unsupervised Trace-SPC Fault Detection Solution Based on Representation Learning and Isolation Forest
Presenter: Haixiang Qiu, Semitronix Corporation
Abstract: Wafer manufacturing is a complex process involving hundreds of process steps. Detecting and identifying potential anomalies and malfunctions in sensor parameters are crucial for improving production yield. However, traditional rule-based or statistical methods fail to meet the requirements of accuracy and efficiency. To address this issue, we propose an innovative model called RLIF-Net that combines deep learning with Isolation Forest. The deep learning module is used to extract multi-dimensional feature vectors at each timestamp, while the Isolation Forest module takes the multi-dimensional feature vectors at each timestamp as input for anomaly detection in the timestamp dimension. We conducted experiments using a real industrial dataset and compared our model with several state-of-the-art models. The results demonstrate that our model exhibits strong learning and representation capabilities, enabling it to learn from large amounts of data and identify complex anomaly patterns.
Robust Wafer Classification with Imperfectly Labeled Data
Invited Speaker: Xin Li, Duke Kunshan University