A Novel Automatic Placement Generation Tool for Current Mirror in Analog Circuits
Presenter: Yuejiao Wang, Fudan University
Abstract: Analog layout design lacks effective automation tools and is still performed manually. For the placement of current mirror which is one of the most important building blocks in the analog circuit, existing methods typically rely on the common centroid technique, and do not include cascode current mirrors with various transistor lengths. This paper developed an automatic placement generation tool utilizing procedural method, which is applicable to all current mirror variants. This tool generates a diverse set of valuable solutions and automatically performs de-duplication and filtering. The solutions exhibit optimal aspect ratios and area occupancy, with improved routability and reduced wire length during routing.
Differentiable Rectilinear Steiner Trees for Analytical Placement
Presenter: Zhiyang Chen, Tsinghua University
Abstract: Placement for very large-scale integrated (VLSI) circuits is a crucial stage for design closure. The wirelength model is a critical ingredient in modern analytical placers, which significantly impacts the overall design quality. Various models have been proposed to smoothly approximate the half-perimeter wirelength (HPWL), such as weighted average. However, during the routing stage, nets are typically routed by rectilinear Steiner trees (RSMT). It has been empirically shown that HPWL cannot accurately approximate the routing wirelength, which induces notable sub-optimality. In this work, we analyze the approximation errors of HPWL model, and theoretically prove the effectiveness of the RSMT-based wirelength model. Moreover, we propose the first differentiable RSMT wirelength model based on the classic RSMT algorithm, which is integrated into the state-of-the-art analytical placer. Experimental results show that our wirelength model improves RSMT wirelength by ~3.5% on average compared with the HPWL-based model on ISPD-2005 placement benchmarks.
Effective Legalization with Cell Version Replacement for Hybrid-Row-Height Circuit Designs
Presenter: Hong Liu, Southeast University
Abstract: In traditional circuit designs, rows within the placement region typically have uniform height. However, a novel hybrid-row-height design paradigm has recently emerged, integrating tall and short rows within the placement region. This innovative approach enhances optimization opportunities for power, performance, and area. Nevertheless, it poses new challenges in placement legalization due to the heterogeneous row and cell structures. Therefore, this paper proposes an effective legalization algorithm with cell version replacement for hybrid-row-height circuit designs. Our approach takes full advantage of multiple versions of the same cell, each with varying dimensions (heights and widths), to incorporate a mechanism for cell version replacement throughout the legalization process. This consideration can help to obtain a legal placement that more closely resembles the global placement, consequently mitigating the increase in half-perimeter wirelength (HPWL). Simultaneously, it can ensure that the tall-row and short-row resources are not overused, avoiding a non-legal placement. Compared with a baseline and a recent work, experimental results show that our algorithm can achieve the smallest HPWL and runtime.
Chiplet Placement Order Exploration Based on Learning to Rank with Graph Representation
Presenter: Zhihui Deng, Shanghai Jiao Tong University
Abstract: Chiplet-based systems, integrating various silicon dies manufactured at different integrated circuit technology nodes on a carrier interposer, have garnered significant attention in recent years due to their cost-effectiveness and competitive performance. The widespread adoption of reinforcement learning as a sequential placement method has introduced a new challenge in determining the optimal placement order for each chiplet. The order in which chiplets are placed on the interposer influences the spatial resources available for earlier and later placed chiplets, making the placement results highly sensitive to the sequence of chiplet placement. To address these challenges, we propose a learning to rank approach with graph representation, building upon the reinforcement learning framework RLPlanner. This method aims to select the optimal chiplet placement order for each chiplet-based system. Experimental results demonstrate that compared to placement order obtained solely based on the descending order of the chiplet area and the number of interconnect wires between the chiplets, utilizing the placement order obtained from the learning to rank network leads to further improvements in system temperature and inter-chiplet wirelength. Specifically, applying the top-ranked placement order obtained from the learning to rank network results in a 10.05% reduction in total inter-chiplet wirelength and a 1.01% improvement in peak system temperature during the chiplet placement process.
Subgraph Matching with Diversity Handling and Its Applications to PCB Placement
Presenter: Haiming Lin, Fuzhou University
Abstract: Printed circuit board (PCB) placement is a critical stage in industrial chip design, which still heavily relies on manual methods, leading to substantial design time consumption. Given the frequent occurrence of similar or identical modules in different PCB designs, the reuse of placements emerges as a promising avenue to enhance the efficiency of PCB placement. In this paper, we propose a subgraph matching based reference placement algorithm to achieve PCB placement reuse, thereby improving placement efficiency. We first take the netlist of the already placed and unplaced circuits as input and abstract them into graphs. Then, we construct and filter candidate spaces based on the characteristics of components and nets. In the process of filtering candidate spaces, we adopt diversity handling that includes cut edges and block nodes to ensure the proposed algorithm can handle inexact matching. Finally, we introduce virtual nodes to construct a matching tree using a combination of depth-first search (DFS) and breadth-first search (BFS), and then perform hierarchical matching based on this matching tree to complete the subgraph matching and obtain the placement results. Experimental results show that in large-scale PCB cases, our algorithm runs much faster than the state-of-the-art works. Particularly, the matching rate of our algorithm is almost 100% for the tested cases.
A Novel Automatic Placement Generation Tool for Current Mirror in Analog Circuits
Presenter: Yuejiao Wang, Fudan University