EDA² | ISEDA 2024

The Breakthrough in Testing

Session Chair: Huawei Li, Institute of Computing Technology, Chinese Academy of Sciences

Abstract: In many applications, for example in autonomous driving, integrated systems face stringent requirements concerning performance, power, functional safety, and reliability. This is particularly true for the on-chip communication. On the other hand, small data deviations may be acceptable within a certain range, which offers opportunities for optimization. Existing solutions for system-level interconnects comprise bus encoding for performance and power, as well as error correcting codes and periodic maintenance tests for functional safety. However, these techniques also lead to additional stress and may induce crosstalk between interconnect lines, which in turn can increase electromigration and reduce the overall lifetime of the system. In this contribution, we will show how safety and reliability considerations can be properly integrated into the design of communication and test schemes.

Abstract: Many defects during manufacturing, operation or in the wear-out phase result in delay faults and particularly Small Delay Faults (SDF) where the additional delay of a component is smaller than the clock period. SDFs are only visible at the outputs of long paths and are especially hard to detect in circuits suffering from timing variations. Major sources of timing variations are process variations (P), voltage fluctuations (V), shifts in temperature (T), and the circuit age (A). Consequently, a robust test set must be effective for all possible combinations of operational conditions, which is rarely feasible during manufacturing. In the field, these test patterns would have to be applied as a functional test by templates or as a periodic Built-In Self-Test (BIST), which is not practical. In this contribution, techniques are discussed to minimize the number of conditions, the required test sets and the test time.

Abstract: This paper presents a highly efficient and accurate approach for detecting observability and assessing testability in contemporary logic circuits with growing size and heightened complexity, especially for MCUs or SoCs used in the automotive industry. The algorithm incorporated in this methodology also mitigates the accuracy loss caused by reconvergent fan-outs. The proposed observability correction method results in a significant improvement in rectifying erroneous node observability calculations compared to existing algorithms while achieving faster execution times. In the context of simulation-based testability and observability evaluations, we also introduce a constant folding algorithm that enables rapid MFFC calculation. By incorporating levelized data parallelism in a two-phase computation process (comprising forward and backward propagation), our approach achieves a performance speedup of more than two orders of magnitude compared to mainstream SAT solver-based techniques and is 50X faster than the fault injection engine of a commercial tool.

Abstract: In System-on-Chip (SOC) testing, various fault models are created to simulate the actual behaviors of faults. Based on these models, comprehensive test patterns are generated to test the SOC thoroughly. This ensures that the SOC can identify and resolve any potential issues that may arise during its operation.
During the test pattern generation (TPG) process, generating a test pattern to detect part of faults can be very difficult due to various limitations, including design complexity, limited pattern search, and fault modeling. This paper refers to these types of faults as Hard-to-Detect faults (HDFs). The presence of HDFs results in a loss of test coverage and consumes significant computing resources during TPG.

Abstract: With the widespread application of chips in mission_x0002_critical and safety-critical fields, ensuring that chips do not fail during operation has become crucial. However, the increasing number of hard-to-detect latent defects within chips is one of the main factors affecting the quality and reliability of the chip. In this paper, we propose a method to generate latent defect acceleration patterns based on path critical defect locations. When the latent defect appears in different defect locations of the path, the delay of the path will be affected differently. In the proposed method, defect criticality is used to measure the impact of latent defects at different locations on path delay. Critical latent defect locations of the path are selected based on the value of defect criticality. Then the user-defined-faultmodel (UDFM) is used to generate the latent defect acceleration pattern with the goal of maximizing the electrical activity of the critical latent defect location in the path. Experimental results show that the patterns generated using our method achieves an average of 34.9% increase in current through path critical latent defect locations compared to transition patterns.

Abstract: With the rapid increase in the scale of Very Large Scale Integration (VLSI), the runtime of fault simulation becomes a crucial issue during the test development phase of the VLSI design process. Various acceleration techniques have been proposed across different dimensions. However, a single technique may struggle to comprehensively address the multiple challenges in the fault simulation domain. This paper optimizes existing multi-threaded fault simulation algorithms on ARM multi-core processors. Firstly, the baseline single-threaded fault simulation algorithm was implemented with various optimization techniques such as event-driven, fault collapsing, and ARM NEON. Secondly, based on the analysis of uneven workloads in a previous multi-threaded algorithm, we present a fault-block allocation strategy to balance workloads among threads, which adopts parallel pattern single fault propagation and FFR-based fault sorting as well, to effectively reduce simulation path disparities among different threads. Experimental results conducted on the Kunpeng 920 processor demonstrate the effectiveness of the implemented algorithm with integrated multiple optimization techniques.