Static Timing Analysis Acceleration to Attack Process Corner Explosion by Matrix Filling Prediction
Presenter: Longze Wang, Beihang University
Abstract: Static timing analysis (STA) is a highly effective procedure required for modern advanced nanoscale integrated circuit design. However,the increasing number of process corners has made performing STA analysis at each physical design stage time-consuming. To enhance efficiency, we propose MCSTA, a point-wise imputation method, to predict timing path delay under different process corners. We formulate it as a partial matrix completion problem and solve it using a neural network-based timing prediction algorithm. Unlike previous methods that rely on full-timing simulations under the specific process corner, our algorithm captures timing information from only a few timing paths, significantly reducing run time overhead. We further optimize timing prediction accuracy using autoencoders to capture relationships between timing paths and process corners. Additionally, we introduce an active learning algorithm adapted for point-wise imputation to utilize timing information from previous design stages, minimizing the required number of timing simulations and improving prediction performance. Experimental results show that our method achieves nearly 100% accuracy with a limited number of path timings while reducing run time overhead by orders of magnitude compared to conventional STA analysis.
Aging-aware Path Timing Prediction via Graph Representation Learning
Presenter: Shuhao Jia, Southeast University
Abstract: In advanced CMOS technology, aging degradation dominated by Negative Bias Temperature Instability (NBTI) has emerged as a significant challenge for the timing closure of circuits. Accurate aging-aware static timing analysis (STA) at the early design phase is critical for establishing appropriate timing margins to ensure circuit reliability throughout the chip lifecycle. Traditional aging-aware timing analysis flows find it difficult to achieve a tradeoff between computational overhead and accuracy. In this paper, we propose an aging-aware path timing prediction framework via graph representation learning. We customize a graph transformer network (GTN) to generate efficient path graph representation with global attention mechanism. Experimental results demonstrate that our proposed framework can obtain accurate timing path prediction with MAPE score of 3.75%, and can achieve acceleration of over 7000 times compared to SPICE simulation with acceptable accuracy loss.
An Efficient Statistical Clock Skew Analysis Method for Cock Trees
Presenter: Ziyin Cui, Southeast University
Abstract: Increasing process variability poses great challenge in 2D/3D high-performance clock network design. The variation of deivce, interconnect and TSV lead to the clock skew variation. However, in most prior models, the variation was not considered comprehensively, where the effect of the equivalent capacitance variation of the interconnect/TSV on the delay of the device was ignored, leading to poor accuracy for clock tree delay variation. In this work, an efficient statistical clock skew analysis method for clock trees is proposed, which considers the variations of device, interconnect, and TSV in 2D/3D clock trees together, and considers the cap variation impact on device variation during the bottom up propagation algorithm. The proposed model was validated under TSMC 22nm process by 3D clock trees implemented for artifical H-tree structed cases and ISCAS’89 benchmarks. Our model demonstrates excellent agreement with golden Monte Carlo simulation results in terms of the standard deviation of maximum clock skew with the average error of 2.35% while achieves 1400 times speed up. Comparing with competitive works, our model achieves 1.7 times accuracy improvement with comparative simulation effort.
An Efficient Aged Timing Analysis Method for Digital Integrated Circuit under NBTI Effect
Presenter: Yang Zhang, Xidian University
Abstract: With the continuous development of semiconductor technology, the performance and integration of integrated circuits (ICs) have been continuously improved. However, below the 65nm technology node, one of the aged effects of chips, Negative Bias Temperature Instability (NBTI) effect, has become an important factor affecting the performance and reliability of digital integrated circuits. This paper proposes an efficient aged timing analysis method for digital integrated circuit under NBTI effect. The method characterizes standard-cell aged library under a small number of typical input signal probabilities. Based on the established standard-cell aged library, timing model for perceiving NBTI aged is constructed through machine learning regression. The timing model established in this paper includes the mapping relationship between aged -related parameters and corresponding aged timing, with the input signal probability, input signal transition time, and output load capacitance of the cell as inputs, and the delay or output transition time of the cell as output. Based on the established timing model for perceiving NBTI aged, timing simulation of each cell in digital integrated circuits can be performed after degradation. Experimental results indicate that compared to existing methods, the approach presented in this paper reduces aged library usage by approximately 70% while only introducing small timing simulation error.
SD-SSTA: Statistical Static Time Analysis Algorithm Considering Skewed Distribution
Presenter: Fuxing Deng, China University of Petroleum
Abstract: Static Timing Analysis (STA) is one of the most widely used and successful analysis engines in digital circuit design in recent years. However, the Deterministic Static Timing Analysis (DSTA) does not take into account the effect of process parameter variability on circuit performance, which arouses people's attention to the ability of STA to effectively simulate statistical changes. Therefore, Statistical Static Timing Analysis (SSTA) has been proposed and extensively studied. Traditional SSTA algorithms, such as probabilistic propagation based on Gaussian distribution and Monte Carlo simulation, cannot achieve a high accuracy and good performance. In this paper, a SSTA algorithm considering skew distribution, SD-SSTA, is proposed, which successfully realizes accurate calculation of arrival time and timing margin, and has excellent performance. The paper makes three contributions. (1) We convert the non-Gaussian distribution into a Gaussian Mixture Model (GMM), which fits the real result better than the traditional SSTA algorithms. (2) We consider the influence of skew and introduce Skew Adjustment Factor (SAF) into the calculation of timing margin to ensure that the results are more realistic. (3) We use the name mapping method to reduce the memory consumption of the algorithm, which further improves the algorithm memory performance. Compared with SSTA algorithm based on Gaussian distribution, SD-SSTA algorithm has excellent performance in both accuracy and performance.
Static Timing Analysis Acceleration to Attack Process Corner Explosion by Matrix Filling Prediction
Presenter: Longze Wang, Beihang University