EDA² | ISEDA 2024

Thermal Management at Chip Level

Abstract: This paper presents a 3D Interlayer Cooling Emulator written in C++ and python language, in which a common Compact Transient Thermal Modeling (CTTM) of solids and fluids based on an equivalent circuit of convection thermal resistances is proposed. Compared to the state of art tools such as 3D-ICE, our previous in-house 3DDCTM fast thermal simulation tool, the present method has the ability of calculating the heat transfer between solid and fluid much more accurately by solving the unsteady heat convection-diffusion problem in the whole domain, rather than using a semi-empirical correlation. To verify the correctness of the proposed method, three typical tests including 3D interlayer cooling are implemented and maximum relative deviation of the junction temperature is 2.83% compared with results from commercial tools demonstrating the high precision of the present tool. Moreover, the proposed Emulator could greatly reduce the calculation time and in the test about 157 times faster than commercial tools are observed.

Abstract: This paper proposes a rectangular approximation method for curved-shape power density to rapidly calculate the temperature profile of the entire chip by using the 2D thermal model with the effective thermal characteristic length. The proposed method employs rectangular blocks to approximate the non-rectangular power density areas, thereby enabling the utilization of stepwise integration for the determination of the cosine series coefficients. In contrast to the conventional grid mesh approach, this rectangular approximation significantly reduces the number of required mesh elements, thus considerably enhancing computational efficiency. Numerical results reveal that the proposed method achieves a speed improvement ranging from 94× to 195× over the traditional grid technique, while maintaining comparable accuracy. Furthermore, the maximum absolute error observed in temperature predictions is limited to a mere 0.37K.

Abstract: Modern high performance computing chips, such as SoC and CPU, are requiring higher hash rate, which accelerates the integration level of integrated circuits. As the Dennard's law no longer holds, the power density of integrated circuits also increases with the level of integration, which results in the fact that the thermal issue is becoming one of the most important issues limiting the development of integrated circuits. To tackle this problem, a fast thermal analysis methodology for integrated circuits is needed. In this paper, we presents a fast on-chip thermal analysis methodology using a hybrid thermal model. The hybrid thermal model is the combination of the detailed on-chip model and the compact model for the package. We propose a novel thermal analysis flow that separates the construction and reduction of the package from the on-chip thermal simulation. Once the compact thermal model of the package has been extracted, we can combine it with any detailed model of the chip to perform fast thermal simulation. The experimental results show that our hybrid model achieves a 28X speedup without any accuracy loss.

Abstract: Thermal simulation plays a fundamental role in the thermal design of integrated circuits, especially 3D ICs. Current simulators require significant runtime for high-resolution simulation, and dismiss the complex nonlinear thermal effects, such as nonlinear thermal conductivity and leakage power. To address these issues, we propose ATSim3D, a thermal simulator for simulating the steady-state temperature profile of nonlinear and heterogeneous 3D IC systems. We utilize the global-local approach, combining a compact thermal model at the global level, and a finite volume method at the local level. We tackle the nonlinear effects with Kirchhoff transformation and iteration. ATSim3D enables local-level parallelization that helps achieve an average speedup of 40× compared to COMSOL, with a relative error <3% and a state-of-the-art resolution of 4096 × 4096, holding promise for enhancing thermal-aware design in 3D ICs.

Abstract: In this paper, an efficient domain decomposition and reduction (DDR) method is proposed for thermal simulation and design of 2.5D heterogeneous integration. Firstly, the DDR method decomposes the integrated system into the core area and the non-core area. Then, the thermal impact of non-core area is represented by the equivalent coupling matrix built up on the interface of two areas, which contributes to confining the solution domain from the whole system to the core area. By this means, the DDR method achieves significant speed-up in the computational efficiency. The accuracy and efficiency of the proposed method is validated through the numerical example, where a 10x speed-up is achieved comparing with the commercial software.