A Neural Network-based Framework for Accelerated Device-Circuit Electrothermal Co-Simulations in GAAFETs
Presenter: Hengyi Liu, Peking University
Abstract: In this work, an efficient electro-thermal coupling model is developed and validated for 3nm Gate-all-around field effect transistors (GAAFET), which combines the artificial neural network (ANN) model for characterizing electrical properties of devices and a multi-stage RC thermal model with geometry dependence. The temperature rise induced by the self-heating effect (SHE) of the device is evaluated by the RC thermal model and feedback into the ANN model for self-consistent electrothermal interactions, and the number of hidden layers and neural nodes in the ANN model has a significant influence on the simulation accuracy and efficiency. A remarkable acceleration with an acceptable accuracy of electrothermal co-simulation compared with that of the BSIM-CMG circuit simulation framework can be observed, which provides a desirable scheme for thermal-aware reliability assessment at the device-circuit level.
Automatic Design of Structural Parameters for GaN HEMT Using Genetic Algorithm and Artificial Neural Networks
Presenter: Wei Du, Nanjing University of Posts and Telecommunications
Abstract: In this paper, an automatic optimization technique of structural parameters for gallium nitride high-electron-mobility transistors (GaN HEMT) is proposed. Given the design targets, including breakdown voltage (BV) and specific on-resistance (Ron,sp), this technique can provide the structural parameters of GaN HEMT to meet the targets based on automatic iteration and optimize process using artificial neural networks (ANN) and genetic algorithms (GA). The results show that, when evaluated through technology computer-aided design (TCAD) simulations, designs obtained from the proposed technique deviate from the expected specifications by 2.6% and 0.98%, respectively. Additionally, the efficiency of the proposed method is reflected in its runtime, with the automated design time for each case is within 2 minutes. We believe that the design approach is crucial in accelerating the design closure for GaN transistors.
Atomic Level to Device Level Simulation of Transistor’s Reliability
Presenter: Yue-Yang Liu, Institute of Semiconductors, Chinese Academy of Sciences
Abstract: Reliability simulation and design is becoming more and more important with the shrinking of device size and advancing of device architecture. However, the traditional simulation tools are not catching up with the increasing demanding on accuracy and universality, due to the strong reliance on empirical/fitted parameters and oversimplified/phenomenological models. It is highly anticipated to improve the traditional tools by integrating with atomistic simulations and by developing more accurate physical models for various reliability issues.
At atomic level, we can not only calculate the parameters for materials and interfaces accurately, but also reveal the microscopic processes or physical mechanisms vividly. Take the bias temperature instability (BTI) issue for example, whose physical origin is defect induced charge trapping and emission, we can conduct first-principles calculations on realistic semiconductor-dielectric interface models (e.g. Si/SiO2/HfO2), and calculate the key quantities including band alignments, defect energy levels, charge induced reorganization energies, and coupling strength between electronic states. Combing these parameters with charge transfer theories such as Marcus theory and NMP theory, we can obtain the exact charge trapping/emission rates of various defects in a transistor. These rates can be finally put into compact models to generate the macroscopic appearance of reliability issues, e.g. the threshold voltage shift.
For the hot carrier degradation (HCD) issue, whose physical origin is carrier injection induced defect generation, atomic level simulation can explicitly show which kind of local structure is more likely to be damaged by carriers, how large the energy barrier for defect generation is, how often the carriers of various energies can interact with the defect precursor, and what is the final path of defect generation. The time-dependent density functional theory (TDDFT) allows us to observe the whole process of defect generation directly at real-time. Moreover, the parameters extracted from atomic simulation can be combined with TCAD simulation and physical models to explain the experimental data, and it has been demonstrated by us and collaborators that the hot carrier degradation experimental data can be well modeled to cover a broad range of technologies.
Heat Generation Counted by Phonon Absorption and Emission in GAA FET under the Framework of Non-Equilibrium Green's Function Method
Presenter: Hongwei Zhou, Beihang University
Abstract: As the most promising device beyond FinFET technology, the Gate-All-Around (GAA) field effect transistor (FET) shows excellent electrical characteristics, but also suffers severe self-heating effects, which compromise the performance and reliability of the device. The commonly used Joule heat model fails to investigate the thermal properties of nanoscale devices, and a rigorous treatment of heat generation by counting phonon absorption and emission is demanded. In this paper, we build such a heat generation model for Si GAA nanowire FETs based on the Non-equilibrium Green's function (NEGF) method with the accurate electron-phonon interaction. Both the acoustic phonon scattering and the optical phonon scattering are considered under the self-consistent Born approximation. Since the simple geometry of GAA FETs, an uncoupled mode space approach is adequate and utilized, which alleviates the computation burden dramatically. The Fourier heat equation which takes proposed heat generation model as the heat source is employed in the simulation. The simulation result shows the role of phonon scattering when compared with ballistic transport. The heat source we obtained exhibits similar characteristics to that of the Joule heat model but with a much smaller magnitude. It is also observed that as the channel length decreases, the ratio of heat dissipated in the device decreases, which means that the validity of the Joule heat model becomes even weaker.
Virtual Fab Coupled Physics-based Simulation Design of sub-2nm node 3D Heterogeneous 6T SRAM, with Vertical Si GAA CFET and CAA IGZO Pass Gates
Presenter: Zhaohai Di, Institute of Microelectronics of the Chinese Academy of Sciences
Abstract: In this work, we propose an all-vertical-transistor based 3D heterogeneous 6T SRAM design. Self-align Si vertical gate all-around (vGAA) FEOL CFET inverters and vertical channel all around (vCAA) BEOL-compatible IGZO pass gates (PG) are stacked vertically again in 3 layers within a 2T footprint area. State-of-the-art Virtual Fab process emulation validates the hetero-integration flow and generate near realistic geometry of not only the transistor but also the interconnect of a 6T SRAM cell. Furthermore, by physics based simulation augmented fine tuning and extending the experimental validated device compact model and the interconnect RC, geometry- and parasitic-aware device to circuit DTCO analysis of the 3D heterogeneous 6T SRAM is performed. The hetero-integration of IGZO vCAA PG and vGAA CFET inverters showed 59% Read Static Noise Margin (RSNM) enhancement, 86% static leakage power reduction, and 53% area reduction.
Optimization of Breakdown Characteristic for SiC MOSFETs by Self-developed Simulator
Presenter: Yuanzhao Hu, Peking University
Abstract: We have developed a simulator based on semi-classical transport models, which include mobility,generation, and recombination models, to study and optimize the performance and breakdown characteristics of 4H-silicon carbide (4H-SiC) MOSFETs. This simulator matches well with both experimental and commercial TCAD results, proving to be a stable and reliable tool.With this simulator, we studied the dependence of the breakdown voltage on the temperature and the structural parameters of the device, and provided an optimization for enhancing the breakdown voltage. Our findings reveal that adjusting the device structure influences the breakdown voltage more than regulating the temperature.
A Neural Network-based Framework for Accelerated Device-Circuit Electrothermal Co-Simulations in GAAFETs
Presenter: Hengyi Liu, Peking University