EDA² | ISEDA 2024

Analog Insights: New Waves on Simulation and Analysis

Abstract: In this talk, we briefly introduce a mixed signal simulator from our company, MSIM. The interface between the analog and digital domains is where the complexity arises. Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) play a pivotal role at this interface, translating between the continuous nature of analog signals and the discrete steps of digital signals. MSIM provides the interface elements (IEs), which encapsulate the A2D and D2A components, facilitating the labor needed for the user to design the system. MSIM elaborately handles various difficulties in mixed signal simulation, especially in the interaction between analog and digital counterparts. It not only models these conversion processes accurately but also handles the timing and synchronization of the signals across both domains.

Abstract: This paper proposes an automated generation method which encompasses the entire process from performance specifications to layout for the fully differential gain-boosted operational amplifier (op-amp). At the schematic level, this process uses the gm/ID methodology to automatically explore solution spaces and determine dimension(W/L) of transistors to meet performance constraints. By transition of pre-computed lookup table across technologies, it achieves design migration. At the layout level, leveraging Tsinghua Electronic Design (TED) enables direct conversion of parameter of circuit into layouts. Experimental results show this process can generate sized circuits and layouts meeting requirements across various technology and performance specification.

Abstract: In the semiconductor storage domain, the swift advancement of Static Random-Access Memory (SRAM) has been significantly accelerated by the extensive adoption of so phisticated SRAM Compiler tools. These instruments enable the rapid generation of tailor-made SRAM memory arrays, effectively addressing specific design requirements. Nonetheless, the development of comparable compiler technologies for other types of memory, such as Multiple-Time Programmable (MTP) memory, has been notably absent. Our study fills this void by introducing a groundbreaking MTP Compiler that is both parameter-driven and compatible across different processes. Leveraging the capabilities of the TED electronic design au tomation tool, this innovative compiler facilitates the expedited production of MTP circuits and layouts for a broad spectrum of capacities, catering to diverse design needs. Its adaptable architecture is especially proficient at accommodating changes in process nodes, significantly reducing the time and effort required for the development of MTP memory technologies. This advancement streamlining the path from concept to production for MTP memories.

Abstract: In this paper we study an application of Ohlrich's SubGemini algorithm, a subcircuit matching algorithm, to structural modeling and sizing of CMOS analog integrated circuits with emphasis on multiple-stage circuits including Op Amps and low-dropout (LDO) regulators. Structural modeling can help the design of multiple-stage circuits by introducing structural reduction, structural constraint, and structural mapping, enabling design automation in this field with a traceable circuit manipulation track. Given the fact that a large number of CMOS transistor-level components (cells) are frequently used in analog integrated circuit, we propose to create a library for such commonly used cells and develop a hierarchical subcircuit matching engine (by an adaptation of the SubGemini algorithm) to decompose structurally an analog circuit into a cell form assembly. This work can also be considered a structural circuit recognition work, which can be applied to fast macromodel generation and sizing constraint generation. Procedural details are presented and applications are demonstrated.

Abstract: With the development of semiconductor technology, the process nodes are being continually reduced. While digital circuit design has been automated throughout the process, the design of analog circuits still relies on manual design. Hence, there is an urgent need to develop automated design tools for analog circuits to improve productivity. In this paper, we propose a method that combines the advantages of Bayesian optimization and dynamic Monte Carlo tree search to obtain the feasible solution space through adaptive clustering, thereby narrowing the search range of the Bayesian optimization algorithm and improving optimization efficiency. For the Ackley test function, low-noise transconductance amplifier and bandgap voltage reference experiments: in comparison with the Trust Region Bayesian Optimization (TuRBO) that is currently available, the optimization outcomes are enhanced by 20.4% to 46.5%, leading to a speedup of 0.95 to 2.62 times. Additionally, in comparison with the LA-MCTS algorithm, the optimization outcomes are improved by 20.4% to 46.5%, resulting in a speedup of 0.96 to 6.55 times.

Abstract: In this paper, a partial performance tradeoff modeling method is proposed for the hierarchical optimization of large analog systems. The key idea is to extract partial Pareto front model around the optimized block-level target performances instead of extracting the complete one. An iterative method based on Bayesian optimization is further proposed to update the partial model and, simultaneously, optimize the entire system. Our experimental results demonstrate that compared to the state-of_x0002_the-art methods, our proposed method can achieves 3.0´ cost reduction without surrendering any performances.