Session Chair: Yijun Cui, Nanjing University of Aeronautics and Astronautics
Empowering Next Generation IC Design and Manufacturing through Innovation
Invited Speaker: Geng Bai, GWX Technology
Abstract: "This report will focus on how the innovation of EDA tools can inject new vitality into the next-generation IC design and manufacturing, and explore how to improve data integrity and accelerate the design and manufacturing processes under the background of increasing globalization and complexity of IC manufacturing. Additionally, the report will analyze the process of using GPU technology to accelerate optical proximity correction (OPC) and the role of the modular architecture of general-purpose service engines in improving performance and efficiency. By combining embedded AI algorithms with GPU acceleration, unprecedented speed and accuracy can be achieved in computationally intensive tasks. Finally, the report introduces the concept of DTCO into the IC design and manufacturing stages, discussing how it can support manufacturing optimization for IC design. The relevant research results have set new standards for performance, accuracy, and usability in the EDA industry, showcasing the application prospects of technological innovation in the face of challenges. We look forward to discussing the future development trends of EDA tools with industry peers, promoting innovation and cooperation, and jointly ushering in a new era of next-generation IC design and manufacturing."
Adaptive time-stepping technology for CMP simulation efficiency
Presenter: Rui Zhang, Semitronix Corporation
Abstract: As process technology scales down and new materials are introduced, coupled with the escalating complexity of processes, enhancing yield in chip production becomes an increasingly formidable task. The incorporation of an important process, Chemical Mechanical Polishing (CMP), is designed to ensure the controlled surface morphology of each wafer, thereby augmenting chip production yield. Building upon the findings of T. Tugbawa et al., the parameterization of layout pattern feature extraction, in conjunction with the modeling of corresponding process steps in chip production, allows us to simulate and predict the entire process of surface morphology changes during CMP. This paper introduces the development of modeling and prediction software for CMP simulation processes (CMPEXP), grounded in the aforementioned research. An adaptive time step iterative simulation strategy has been implemented in this study, resulting in an enhancement of simulation efficiency by approximately 150% compared to fixed time steps iteration.
Utilizing Neural Networks for Automated Construction of Semi-Physical CMP Models
Presenter: Yue Qian, University of Chinese Academy of Sciences
Abstract: The planarization of chip surface after chemical mechanical planarization is more and more important which may cause DOF, IR drop, timing closure, EM problems. Given that CMP modeling encompasses the integration of multiple complex mechanisms, including physics, chemistry, and materials, enhancing the accuracy of traditional CMP models based solely on physical principles becomes challenging. The empirical relationships and con-stants in semi-physical models are typically manually specified by experts, resulting in minimal automation in model deployment. We propose utilizing neural networks to automate the construction of these relationships, thereby enhancing the automated construction of semi-physical CMP models. It incorporates well-established optimizers to speeds up training and significantly improves model accuracy. Experimental results indicate that our model competes with fully data-driven models, outperforms existing semi-physical models, and achieves a remarkable 30% reduction in RMSE with rapid training (fewer than 200 epochs).
Performance Analysis of Different Processor Architectures Applied to CMP Process Modeling Acceleration
Presenter: Zhirui Niu, University of Chinese Academy of Sciences
Abstract: The current research trend in microelectronics industry focuses on applying deep learning to Electronic Design Automation (EDA) to deal with the increasing computational demands. There is a rising requirement for higher computational power with the escalation of chip design scale and the complexity of chip performance analysis, thus the utilization of Data Computing Unit (DCU) or Graphics Processing Unit (GPU) with powerful parallel computing capabilities for acceleration becomes imperative. The Hygon Z100 DCU, a processor dedicated for large-scale data processing, has been extensively deployed in heterogeneous computing platforms. In this paper, a series of microbenchmark programs are designed based on the architecture of Hygon Z100 DCU and NVIDIA RTX 2080Ti GPU. Additionally, EDA softwares developed by the research group are ported to both computing platforms. The performance differences between the Hygon Z100 and NVIDIA RTX 2080Ti are tested, and their acceleration capabilities in EDA applications are compared. Due to the higher number of stream processors and additional tensor cores dedicated for accelerating matrix operations in the RTX 2080Ti GPU, it demonstrates higher acceleration performance compared with the Hygon Z100 in EDA applications.
Application of a CFD simulation on spin coating process
Presenter: Xinchang Wang, Guangdong Greater Bay Area Institute of Integrated Circuit and System
Abstract: In this study, a three-dimensional spin coating model has been built up to simulation the flow formation process of Lagrange droplets in photoresist coating process. Numerical calculation was performed by using the commercial computational fluid dynamics (CFD) package with a Reynolds-averaged Navier-Stokes (RANS) equation solver and a realizable k_k two-layer model. The effects of the spin speed, dispensed volume, solvent saturated vapor pressure, initial photoresist viscosity on the film thickness and uniformity have been examined with different spin coating process parameters and material parameters. The initial photoresist viscosity and saturation vapor pressure are important parameters that affect the average film thickness. The spin-coating process of a wetting recipe was simulated using the model and compared with an recipe without wetting. The wetting recipe involves spraying 2.5cc of PGMEA solvent during static conditions, followed by the addition of 1cc of Lagrange photoresist droplets within 4.8 seconds. In contrast, the recipe without wetting injects 2cc of droplets at low speed. At the completion of the entire recipe, the wetting recipe exhibits an improved average film thickness compared to the typical recipe, it shows that wetting recipe can realized the purpose of photoresist reduction.
Line Edge Roughness Modeling for Continuous Time-space Resist Simulations
Presenter: Hong Chen, GWX Technology
Abstract: Resist line edge roughness (LER) is generally regarded as noise inherent in every lithography processing step. Current state of art LER simulators model the physical causes of LER rigorously at each step, including the variation in optical source, resist material and PEB/development processes, and by using a set of stochastic, multi-scale numerical algorithms. With a high level of complexity involved, computational cost is often unacceptable for practical usage on larger patterning areas. Another disadvantage of the current LER models requires a significant modification for the existing simulation flow and numerical solvers, incurs a high R&D overhead and difficulties in industrial adoption. This work proposed a semi-empirical but straightforward LER simulation method that works around all the difficulties in current LER modeling. By introducing an appropriate amount of randomness to the system using LER parameters, it is possible to produce the desired LER in a resist simulation. LER is therefore a natural result in a numerical simulation due to the randomness carried by the initial value.
Empowering Next Generation IC Design and Manufacturing through Innovation
Invited Speaker: Geng Bai, GWX Technology
The relevant research results have set new standards for performance, accuracy, and usability in the EDA industry, showcasing the application prospects of technological innovation in the face of challenges. We look forward to discussing the future development trends of EDA tools with industry peers, promoting innovation and cooperation, and jointly ushering in a new era of next-generation IC design and manufacturing."