EDA² | ISEDA 2024

Advanced Tactics in Design Methodology

Abstract: Modern-day control applications increasingly rely on cyber-physical systems (CPS) to implement advanced functionalities. Notable examples within automotive domains include adaptive cruise control, intelligent navigation, and autonomous driving. Leveraging the cloud's virtually infinite storage and computational power proves to be an efficient strategy for executing these sophisticated control algorithms. However, migrating control computations to the cloud introduces new challenges, notably pertaining to security and real-time constraints. We will present an integrated design and optimization methodology tailored for cloud-based control systems. This approach addresses security concerns and other crucial CPS design prerequisites, particularly focusing on ensuring the security and stability mandates of control loops closed over the cloud.

Abstract: With the increasing complexity of integrated circuits, agile hardware design methodologies are crucial. Modern HDLs like Chisel enhance design quality, but manual implementations remain error-prone and time-consuming. Large language models (LLMs) offer potential for design automation through natural language, but face challenges in generating large circuits using Verilog. We evaluate LLM capabilities for Chisel and Verilog generation, demonstrating superior Chisel generation ability. We introduce “ChatChisel,” the first language-based agile hardware design workflow that generates Chisel from language specifications. ChatChisel utilizes four LLM-based modules for decomposing, generating, error-correcting, and composing hardware designs. Techniques like LLM collaboration and RAG enhance ChatChisel's performance. Using only GPT-3.5-turbo, we generated a RISC-V CPU supporting RV32I, pipelining, and dynamic branch prediction, validating our approach. This work automates agile hardware creation with LLMs, significantly reducing design time and improving design quality.

Abstract: As the increasing demand for large and complex signal processing requirements, the efficient and fast design of signal processing circuits becomes an important issues. Agile design offers a new approach for rapid hardware design cycles. While this approach is a standard for software design, how to adapt it to hardware design properly remains an open question. In our work, we propose a framework for agile software and hardware co-design named GraphRTL. The tool addresses the challenge of designing hardware for Digital Signal Processing (DSP). Instead of direct coding and debugging iteration, we employ data flow graphs (DFG) and control flow graphs (CFG) to automatically generate RTL code. The input to GraphRTL is the flow graph of the designed circuit. Subsequently, the tool checks the graphs, reconstructs it, and then translates it into a configuration file for the compiler. Finally, the compiler autonomously generates the corresponding software to hardware code and RTL code. Compared to the traditional design route, GraphRTL enhances design efficiency and broadens the design space. In our experiments, we achieved up to an 70% reduction in design time while maintaining a 5 to 10% reduction in hardware overhead for the designed circuits.

Abstract: The interdependence of various design levels in computing-in-memory (CIM) chips makes optimization at a single level insufficient to achieve the desired performance metrics. Collaborative optimization across different design levels, including algorithms, architecture, circuits, and devices, has emerged as a requisite technique. We have developed a hardware-software co-design tool, CoMN, to facilitate rapid deployment of neural networks on CIM chips, to evaluate and trade-off accuracy and performance, as well as to explore the algorithm-hardware design space. To enhance the usability of CoMN, a graphical user interface has been developed, accessible via the URL http://101.42.97.22:8081/index.html. CoMN is designed not only to enable users to preliminarily assess their concepts without comprehensive knowledge of all CIM chip design intricacies but also to narrow down the scope of hardware optimization, thereby expediting subsequent design stages.

Abstract: Computing-In-Memory (CIM) technology is promising for DNN inference acceleration, in which ReRAM-based crossbars have received extensive attention in various aspects. However, the current model deployment research often neglects the read-write imbalance problem. This work proposes a comprehensive solution of inference optimization for multi-bit ReRAM-based crossbar array accelerator. In fine grain of operation unit (OU), a row and column exchange algorithm called RCSwap is proposed to minimize the difference between the weights before and after update and therefore reduce the program time and energy consumption. And in coarse grain, similarity-based scheduling method is presented to exploit the inter-OU difference for further performance improvement. Experiment results show that the proposed methods combined reduce up to 32% and 34% in time delay and energy consumption for model inference, respectively.