A Parallel Acceleration Technique based on Bordered Block Diagonal Matrix Reordering for Exponential Integrator Method
Presenter: Hang Zhou, Southern University of Science and Technology
Abstract: The exponential integrator (EI) method has proven to be an effective technique to accelerate transient circuit simulation. One core step of EI is the generation of rational Krylov subspace basis by the Arnoldi process, which involves one (exact) LU factorization and many back/forward triangular solves. Traditional parallelization techniques for circuit simulation perform well in accelerating the LU factorization part (the symbolic and numerical factorization) but fall short in parallelizing the triangular solution part. In this paper, we propose a parallel Bordered Block Diagonal (BBD) matrix reordering algorithm and a parallelization based on OpenMP and MPI to accelerate triangular solutions involved in the rational Krylov space construction in EI. Parallelization is achieved by solving corresponding part of solution vector of each diagonal matrix block independently. Numerical experiments shows that our method can achieve 3.3x and 1.9x speedup under shared and distributed memory environment respectively.
P-TICER: An Effective Parallel TICER Acceleration Method for Model Order Reduction
Presenter: Zijia Zhang, Southeast University
Abstract: In the field of post simulation verification in integrated circuit design, Time-Constant Equilibration Reduction (TICER) is a well-known and widely used algorithm for model order reduction. However, the TICER for large-scale circuits is time-consuming. Moreover, there is a contradiction between the node compression ratio and circuit sparsity. In this paper, an effective TICER-based optimization parellel acceleration algorithm called P-TICER is proposed. An adaptive circuit judgment partitioning strategy based on graph partitioning is proposed to partition circuits and perform multi-threaded parallel acceleration. The compression ratio and sparsity of the circuit are optimized and balanced. Moreover, RC-In-RC-Out structure is designed, which is realizable and seamlessly integratable with other simulators as it takes circuit netlists as input and output. We apply P-TICER to the RC circuits with two different types and nodes scale ranging from 40k to 2 million. Experimental results show that compared with the conventional TICER, the proposed P-TICER is up to 24 times faster, while achieving a node compression ratio up to 50% with the relative error remained within 0.2%.
Implementation of Mixed Precision Sparse Matrix Solving in the Large Scale Circuit Transient Simulation
Abstract: We implement mixed precision sparse matrix solver in the transient simulation of analog circuits. In each time step, we need to perform one single precision LU factorization and a few steps of mixed precision iterative refinement. The overall time benefit of mixed precision sparse matrix solver is 10% compared to double precision sparse matrix solver. The sparsity of the matrix plays a significant role in improving the performance of mixed-precision computation.
A Scalable Approach to Efficient Simulation of Multiphase Constant On-Time Buck Converters
Presenter: Xianting Lu, Zhejiang University
Abstract: The growing demands on microprocessors necessitate advancements in power delivery systems, where multiphase interleaved constant on-time (COT) buck converters stand out for their fast response and high efficiency. While simulations of COT buck circuits are crucial for evaluating circuit performance comprehensively, the inherent complexities in designing these circuits present significant challenges. Particularly, COT buck circuits with an increased number of phases exhibit heightened complexity, often leading to simulation issues such as crashes, interruptions, and non-convergence. The absence of a robust and straightforward simulation structure for high-phase-number COT circuits exacerbates these challenges. To mitigate these issues, this paper introduces a novel structure for COT buck circuit modeling that is specifically designed to support phase expansion and facilitate flexible parameter adjustments for generic SPICE level simulator. This structure aims to simplify the simulation process for complex, multiphase COT buck circuits, thereby improving the feasibility and reliability of the simulations. Furthermore, to enhance the stability and performance of the multiphase COT buck circuit, we implement a current balancing technique, ensuring uniform current distribution across all phases during transient responses. Simulation results validate the effectiveness of the proposed COT buck circuit model, which demonstrates adaptability to varying circuit parameters and maintains good performance even as the number of phases increases.
A Wideband Behavioral Model With Multiple States for RF Power Amplifier Based on Improved Recurrent Neural Network
Presenter: Xingyu Tang, Tsinghua University
Abstract: The signal bandwidth of wireless communication systems is increasing with the advent of the fifth/sixth generation (5/6G) communication, leading to strong memory effects and nonlinearity in RF power amplifiers (PAs). Although artificial neural networks (ANNs) and deep neural networks (DNNs) perform well in PA behavioral modeling with high-dimensional inputs, the modeling accuracy and efficiency still have more room to enhance. In this paper, an improved recurrent neural network (IRNN) based PA behavioral model is presented, in which a special inter-middle layer was added between the RNN network and the MLP network to enhance the wideband modeling capability of memory effects and nonlinearity. The proposed IRNN method also introduces multiple states and the output of the RNN network and the MLP network at previous time into the input vectors, so a big improvement in behavior modeling accuracy with reasonable complexity was achieved. Compared with E-ELM, DNN, and conventional RNN methods, this method can achieve a 9.01 to 17.08 dB improvement in modeling accuracy in the form of normalized MSE (NMSE) on average without adding excessive time cost. In addition, it is shown that the model can predict the behavior of the PA under different input power levels and frequencies accurately, revealing that the new modeling methodology provides very efficient and extremely accurate prediction.
CGAT-TICER: A Compressed GAT-based TICER for RC Reduction
Presenter: Yuchao Zhong, Southeast University
Abstract: Model order reduction (MOR) is an effective method to reduce the circuit simulation time. As a conventional MOR method, Time Constant Equilibration Reduction (TICER) is used widely in fast interconnect analysis. Recently GCN-TICER is proposed by converting the node elimination speed-up problem into the classification issue using GCN-based anomaly detection.However, poor accuracy of node classification leads to insufficient efficiency. Besides, numerous unnecessary computations result in the high cost of elimination due to the uncompacted model. In this paper, we propose an improved algorithm CGAT-TICER using an anomaly detection method based on Graph Attention Network(GAT) to improve the accuracy of node classification. At the same time, we discard irrelevant elements to obtain a compressed model,thus reducing the elimination time. We conduct experiments on 6cases ranging from 1,983 to 1,026,495 nodes in size from a clock_x0002_tree network. Experiments show that our algorithm achieves a1.34× to 17.23× speedup compared to TICER, which is twice the SOTA GCN-TICER. The max relative error is less than 1.106%,which is 0.124% to 0.952% larger than TICER but smaller than GCN-TICER.
A Parallel Acceleration Technique based on Bordered Block Diagonal Matrix Reordering for Exponential Integrator Method
Presenter: Hang Zhou, Southern University of Science and Technology