Design the Right Chip and Design the Chip Right with Precision Chip Strategy
Invited Speaker: Ying J Chen, S2C
Abstract: Fast evovling technolies and applications such as RISC-V, Chiplet and AI are making it harder for designers to keep up with the fast changing market demands. As a leading EDA solution leader specializing in functional verfication, S2C will discuss how its Precision Chip strategy can help "Design the Right Chip and Design the Chip Right" and accelerate time-to-market.
An Efficient Circuit Matching Algorithm Based on Hash Extraction of Features
Abstract: In the field of Electronic Design Automation (EDA) tools, the identification of specific circuit configurations from a design is an inevitable requirement. This paper proposes a novel and efficient technique. Through extensive validation, the algorithm demonstrates accurate identification of specific circuit configurations. Moreover, for large designs with millions of instances, when the traversal starting point is also in the millions, the algorithm takes approximately eight hundred seconds to complete. This demonstrates a high level of efficiency.
How Good is Your Property? A New Metric for Formal Property Coverage
Presenter: Qianwen Zhao, The Hong Kong University of Science and Technology (Guangzhou)
Abstract: Formal property verification has been widely used in function verification, where user-specified properties are checked to ensure function correctness. However, as human verification engineers can also make mistakes when writing the properties, it is a general question on how to ensure the quality of formal properties. There are several existing coverage metrics, e.g., cone-of-influence (COI) and ProofCore coverage that assess the quality of properties in the setting of formal property verification. However, they are not sufficient to identify all coverage holes as this paper will show. Therefore, we propose FRCoverage, a new functional coverage metric for formal property verification, which is based on function reduction. Our case study shows that this new coverage metric successfully identifies three coverage holes in the commonly used RISCV-Formal verification framework when it is applied on PicoRV32 processor verification.
Towards Smart Industrial Hardware Formal Verification
Presenter: Hui-Ling Zhen, Huawei
Abstract: Formal verification has emerged as an alternative approach to guaranteeing the quality and accuracy of hardware designs, surpassing the limitations of traditional validation techniques like simulation and testing. However, as the number of state variables in the system increases, the size of the system state space expands exponentially, leading to the inevitable occurrence of the state explosion problem. Unlike the academic community, which has primarily focused on verification techniques, our approach emphasizes more intelligent modeling and data-driven acceleration.
TBPart: An Effective Topological Order Balanced Hypergraph Partitioning Algorithm for VLSI Processor-based Hardware Emulation
Presenter: Jing Tang, Xidian University
Abstract: As the complexity of circuit designs continues growing, processor-based emulation is becoming more and more popular for design verification. In a large-scale design, there are significant dependencies among the basic logic cells, which is represented as cells' topological order if the design is mapped to a graph. During the circuit partitioning stage, assigning the same topological order cells to one processor would significantly increase the delay of scheduling, further degrading the overall performance. However, some well-known partitioners, like hMETIS and PaToH, mainly focus on cut size minimization without considering such topological order balance constraints, which limits their practical usage in processor-based hardware emulation. In this paper, we propose a partitioning algorithm TBPart considering the topological order balance to address the issue of wasting computational resources in hardware emulation. TBPart improves the topological balance of the partitioning results by considering the gain brought by vertices movement in improving the topological balance while also taking into account the cut-size loss, ensuring the quality of the cut-size while improving the topological balance of the partitioning results. We evaluate TBPart using the ISPD98 benchmark tests, and experimental results demonstrate its effectiveness in improving the topological order balance. On average hand, 0.26 times cut-size loss can result in a 2-fold improvement in topological order balance.
Design the Right Chip and Design the Chip Right with Precision Chip Strategy
Invited Speaker: Ying J Chen, S2C