EDA² | ISEDA 2024

Session Details

Technical Session 6

The Open Source EDA Movement

Session Chair: Guojie Luo, Peking University

Open-Source Incubation Ecosystem to Democratize Digital Microfluidics

Invited Speaker: Tsung-Yi Ho, Chinese University of Hong Kong

Abstract: Advances in microfluidic technologies have led to the emergence of biochip devices for automating laboratory procedures in biochemistry and molecular biology. Corresponding systems are revolutionizing a diverse range of applications, e.g. point-of-care clinical diagnostics, drug discovery, and DNA sequencing–with an increasing market. However, continued growth (and larger revenues resulting from technology adoption by pharmaceutical and healthcare companies) depends on advances in chip integration and design-automation tools. Thus, there is a need to deliver the same level of design automation support to the biochip designer that the semiconductor industry now takes for granted. In particular, the design of efficient design automation algorithms for implementing biochemistry protocols to ensure that biochips are as versatile as the macro-labs that they are intended to replace. This talk will first describe technology platforms for accomplishing "biochemistry on a chip", and introduce the audience to both the droplet-based "digital" microfluidics based on electrowetting actuation and flow-based "continuous" microfluidics based on microvalve technology. Next, the presenter will describe system-level synthesis including operation scheduling and resource binding algorithms, and physical-level synthesis includes placement and routing optimizations. Moreover, control synthesis and sensor feedback-based cyberphysical adaptation will be presented. In this way, the audience will see how a "biochip compiler" can translate protocol descriptions provided by an end user (e.g., a chemist or a nurse at a doctor's clinic) to a set of optimized and executable fluidic instructions that will run on the underlying microfluidic platform. Finally, present status and future challenges of the open-source microfluidic ecosystem will be covered.

AiEDA: An Open-source AI-native EDA Library

Invited Speaker: Xingquan Li, Peng Cheng Laboratory

Abstract: Although Artificial Intelligence (AI) has made significant progress in the Electronic Design Automation (EDA) field, specialized research infrastructure remains insufficient. This paper analyzes the elements required for a better integration of AI with EDA, and presents the preliminary framework of our AiEDA library. This library aims to support AI tasks more effectively within EDA by integrating open-source tools, enhancing data management, and adding functional modules for testing and analysis.

An Open-Source Tool to Model and Explore Complex Routing Architecture for FPGA

Presenter: Kaichuang Shi, Fudan University

Abstract: Routing architecture has a large impact on the FPGA performance and area. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs) which is used in VPR. And there are input crossbars inside the logic blocks (LBs). The routing architecture in VPR is not tileable. Besides, it is hard to model the complex routing architecture as in commercial FPGAs. In this paper, we model a tile-based VRB (Versatile Routing Block) architecture which replaces the CBs, SBs and input crossbars to alleviate this problem. All the routing resources are included in the VRBs and many routing features which are used in commercial FPGAs are supported, such as bent wires, nearest neighbor interconnects and two-level mux topology. In addition, VTR 8 is enhanced to support the VRB architecture and we make it open publicly. Experimental results show that the proposed VRB architecture can achieve 8.2% improvement on the critical path delay and 8.4% improvement on the area-delay product compared to the latest two-level mux architecture.

SATGL: an Open-source Graph Learning Toolkit for Boolean Satisfiability

Presenter: Hongtao Cheng, Beijing University of Posts and Telecommunications

Abstract: As the first proven NP-complete problem, the Boolean Satisfiability (SAT) problem holds significant theoretical value and has wide ranging practical applications. It has also led to the development of numerous SAT-related tasks, such as MaxSAT and UNSAT Core prediction. Due to the high complexity of handling these SAT-related tasks and the natural conversion of SAT formulas into graph structures, researchers have recently developed various graph learning methods to assist in prediction. However, these methods are often experimented on different datasets, with different approaches and different tasks, making it challenging to conduct unified evaluations and develop new algorithms. In this paper, we introduce the SATGL toolkit, the first the first open-source graph learning toolkit for the SAT problem. graph learning toolkit for the SAT problem. We expect SATGL to contribute to the advancement of artificial intelligence (AI) for SAT, facilitating SAT solving and new algorithm design.

FlattenRTL: An Open Source Tool for Flattening Verilog Module at RTL Level

Presenter: Ziyue Zheng, The Hong Kong University of Science and Technology (Guangzhou)

Abstract: While hierarchy in the Register-Transfer Level (RTL) makes hardware designs more readable, reusable, and scalable, a flattened design by removing the hierarchy is useful for synthesis, verification, and optimization. For example, a flattened Verilog module can help the verification tools better analyze the dependencies of signals in exact instances. Therefore, a tool to flatten the Verilog modules at the RTL level is helpful in the electronic design automation (EDA) domain. Flattening the Verilog modules is also a challenge with the ever-increasing complexity of hardware designs. According to our experiments, the existing tool to flatten Verilog modules in RTL is a proprietary tool from EDAUtils, which fails to pass the equivalence checking of the flattened module with the original modules in many benchmarks. In this paper, we proposed an innovative open-source tool called FlattenRTL to convert hierarchical RTL Verilog designs into a flattened, single-module form. FlattenRTL removes the hierarchy while preserving its functionality by employing code analysis and manipulation methods. Experimental results illustrate that the flattened modules pass equivalence checking in all benchmarks. In addition, FlattenRTL is more efficient than the existing proprietary Verilog flattening tool.

OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions

Presenter: Jing Mai, Peking University

Abstract: "FPGA macro placement exerts a significant influence on routability and timing closure in FPGA physical design. Macros could subject to cascaded macro constraints and necessitate placement in contiguous sites. Meanwhile, instances could also subject to fence region constraints, permitting placement within designated areas. Such kind of heterogeneity exacerbates the solution space discontinuity and leads to divergence and local optima entrapment.
In this work, we propose a robust multi-electrostatics-based FPGA macro placer OpenPARF 3.0 that can handle the aforementioned constraints efficiently. We adopt a novel multi-electrostatics region model to handle the fence region discontinuity and propose a divergenceaware density weight scheduling scheme that can address the robustness issues effectively. Experimental results demonstrate that our proposed framework can address robustness issues effectively and outperform state-of-the-art placers in both quality and efficiency."