EDA² | ISEDA 2024

New Frontiers in Analog EDA

Abstract: The existing optimization methods for analog circuit optimization, such as Bayesian Optimization and Trust Region based Derivative Free Optimization, suffer from underfitting surrogate models in high-dimensional problems, which leads to inefficient optimization and sub-optimal solutions. We present a novel Gaussian Process enhanced Subspace Derivative Free Optimization method to solve high-dimensional analog circuit optimization problems. High-dimensional promising region is reduced to a 2-D subspace with two pattern vector: the approximate gradient pattern vector and the iterative descent pattern vector. The Gaussian process is used to approximate the gradient pattern for subspace establishment, significantly enhancing the simulation efficiency. A trust region based derivative free optimization method is proposed for exploiting promising regions in effective low-dimensional subspace. The effectiveness of the proposed method is demonstrated on real-life analog circuits, achieving significant simulation number speedup and runtime speedup compared with the state-of-the-art optimization methods.

Abstract: Conventional NSGA-II encounters significant difficulties in automatic tuning of design parameters for analog circuit design. In response, We present KIDEA, an enhancement of NSGA-II through differential evolution, Isolation Forest, and KMeans clustering. Differential evolution improves efficiency and convergence, while Isolation Forest and KMeans jointly elevate the quality of pareto optimal solutions by refining outlier detection and solution clustering. The algorithm is used to tune the design parameters in analog circuit design. Compared to conventional NSGA-II, the results from KIDEA show average dominance improvement of 34.0% and convergence rate improvement of 3.14 times.

Abstract: The sizing of circuit transistors that meet design specifications in analog integrated circuit (IC) traditionally relies on the intuition and experience of human experts, posing challenges that are labor-intensive and time-consuming, particularly as circuit complexity increases. Compared to mainstream optimization algorithms that exhibit slow optimization speeds and unstable solutions when dealing with large-scale analog IC, this study introduces RLCktII, a breakthrough improvement built upon the advanced RLCkt. For the first time, it incorporates an attention mechanism combined with deep reinforcement learning into the domain of automated analog integrated circuit transistor sizing. Through the attention mechanism, it dynamically discerns the most distinctive input data, enhancing the deep reinforcement learning model's capability to handle complex tasks. RLCkt II was evaluated on two industrial scale analog integrated circuits: LDO and R2R. After one and a half days of training, our RLCkt II agent achieved an average improvement of 28.71% and 7.94% in convergence accuracy over the state-of-the-art RLCkt. In the same design tasks, RLCkt II demonstrated a speed advantage nearly a hundred times faster than the Genetic Algorithm (GA) while also ensuring greater design precision.

Abstract: This paper presents an automated design method for a Strong-ARM dynamic comparator. By modeling and analyzing, the dynamic characteristics of the dynamic comparator are fitted into static characteristics, which is suitable for automatic sizing design with gm/ID method. The sizes of the transistors could be calculated by modeling the relationship with the specifications of the comparator, e.g., clock rate, power and input offset voltage. Furthermore, the automation process is implemented through an analog design tool Tsinghua Electronic Design (TED) and the design flow of the Strong-ARM dynamic comparator was verified at 40nm, 65nm and 180nm technologies respectively. Compared to the performance specifications and simulation results of the input offset voltage and power consumption, the maximum errors are approximately 3% and 6%. Among them, the three sets of power consumption obtained from simulation are all lower than the performance specifications.

Abstract: The automatic synthesis of operational amplifiers (opamps) is in high demand to meet the diverse performance requirements of a wide range of analog circuit applications. However, existing opamp topology synthesis methods neglect circuit performance while generating circuit representations, resulting in suboptimal efficiency. To address this issue, this paper proposes a novel opamp topology optimization approach based on a performance-aware topology representation. Specifically, topology information is captured using a customized graph neural network (GNN), while performance information is incorporated by training the GNN for performance prediction through supervised learning. By combining this performance-aware representation with the genetic algorithm, an efficient opamp topology optimization method is developed. Experimental results demonstrate that our approach outperforms state-of-the-art methods in terms of both optimization efficiency and results.

Abstract: Traditional optimization algorithms suffer performance decline in high-dimensional optimization problems, such as analog circuit design optimization. Adapting existing algorithms to parallel computing environments is a critical challenge. Therefore we propose a parallel Trust Region Bayesian Optimization(TuRBO) algorithm. This algorithm operates in parallel on different trust regions, utilizing a Multi-Armed Bandit algorithm for intelligent sampling to accelerate parameter optimization. Circuit experimental results demonstrate the advantages of this algorithm. Compared to Differential Evolution, Particle Swarm Optimization, Naive Bayesian, High-Dimensional Batch Bayesian Processing, and TuRBO algorithms, the circuit performance achieves improvements ranging from 3.7\% to 98.2\%. Compared to TuRBO, it achieves acceleration ratios in terms of iteration numbers ranging from 1.19× to 1.31×, and in terms of algorithm runtime ranging from 1.21× to 2.25×.