| Time | Title | Speaker |
| 13:30-13:35 | Opening Remarks | Zhufei Chu (Ningbo University) |
| 13:35-14:00 | LLM-based Verilog RTL coding assistant | Pei-Hsin Ho (UniVista) |
| 14:00-14:25 | Smart Verification leveraging PSS | Zhenghua Qi (X-EPIC) |
| 14:25-14:50 | Development and Challenges of Logic Synthesis Tools | Sherry Yang (Hangzhou Dianzi University) |
| 14:50-15:15 | Coffee Break | |
| 15:15-15:40 | Large Circuit Model | Qiang Xu (The Chinese University of Hong Kong) |
| 15:40-16:05 | Logic Optimization Based on Representation Learning | Min Li (Huawei Noah’s Ark Lab) |
| 16:05-16:30 | Quantum Computing Programming Language Based on Coq and Formal Verification of Quantum Programs | Gang Chen (Nanjing University of Aeronautics and Astronautics) |
| 16:30-17:30 | Panel: The Challenges and Opportunities of Digital Circuit Design and Verification in the Era of Large Models | Moderator: Qiang Xu (The Chinese University of Hong Kong) Panelist： Pei-Hsin Ho (UniVista) Zhenghua Qi (X-EPIC) Sherry Yang (Hangzhou Dianzi University) Min Li (Huawei Noah’s Ark Lab) ... |
| 17:30-17:35 | Closing | Zhufei Chu (Ningbo University) |
| Time | Title | Speaker |
| 13:30-13:35 | Opening Remarks | Hailong YAO (University of Science and Technology Beijing) |
| 13:35-14:00 | Multi-objective Design Space Optimization in Logic Synthesis | Ji LI (Shenzhen Giga Design Automation Co., Ltd) |
| 14:00-14:25 | New Challenges in VLSI Placement and Routing Tools | Xiaojian YANG(LEDA Technology Inc.) |
| 14:25-14:50 | STA Technologis and Challenges in Advanced Technology Nodes | Chao YAN(Zhejiang Hexin Industrial Software Inc) |
| 14:50-15:15 | Prospects of Physical Implementation and Design Methodology for 3DIC | Xiaoming LIU (Empyrean Technology) |
| 15:15-15:40 | 3DIC Design & Package Challenges to Signoff EDA Tool | Sheng HAN (PHLEXING Technology Co., Ltd.) |
| 15:40-16:00 | Coffee Break | |
| 16:00-17:00 | Closed-door Seminar | |
| Time | Title | Speaker |
| 14:00-14:05 | Opening Remarks | Lan Chen (IME, CAS) |
| 14:05-14:25 | Quantum Mechanical Correction Models and Computational Methods for Semiconductor Devices | Tao Cui (AMSS, CAS) |
| 14:25-14:45 | Sub-10 nm Atomistic TCAD Based on Non-von Neumann ASIC | Jie Liu (HNU) |
| 14:45-15:05 | Large Scale VLSI Mask Optimization | Bei Yu (CUHK) |
| 15:05-15:25 | TBD | TBD (Primarius) |
| 15:25-15:45 | Coffee Break | |
| 15:45-16:05 | AI Enabled Design to Contour Mechanism for Design Manufacturability Check | Shengrui Zhang (DJEL) |
| 16:05-16:25 | TBD | Ya Lu (Huawei) |
| 16:25-16:55 | Discussion | |
| 16:55-17:00 | Closing | Lan Chen (IME,CAS) |
More workshops will be updated soon.