Invited Speakers
In Alphabet Order of Last Name
Mr. Brophy, Dennis
Bio
Dennis Brophy is Vice President of Standards for the IEEE Council on Electronic Design Automation, and serves as Chair of the IEEE Design Automation Standards Committee. He is also Director of Ecosystems at Siemens EDA, leading global ecosystem and interoperability initiatives for digital verification technologies. Dennis has over 46 years of experience in the electronic design automation industry and holds a B.S. in Electrical Engineering and Computer Engineering from the University of California, Davis.
Talk Title
EDA at Inflection Points: The Critical Role of Open Standards from Languages to Agentic AI
Abstract
Over the past five decades, electronic design automation has advanced through a series of inflection points driven by rising complexity and the need for interoperability. From the early emergence of SPICE as an open academic technology, through the standardization of design and verification languages such as VHDL, Verilog, SystemVerilog, and SystemC, open standards have repeatedly enabled EDA innovation to scale globally across tools, companies, geographies and invite academic exploration. This talk reflects on how IEEE standards helped transform EDA from tool-centric silos into a globally connected engineering ecosystem, and draws parallels to today’s AI era, where agent-based systems and emerging interoperability technologies such as Model Context Protocol are rapidly shaping new workflows. It also discusses emerging challenges around copyright, data usage, and global regulation, and introduces a new IEEE CEDA standards initiative aimed at providing clarity and guidance as the EDA community works to responsibly adopt AI technologies.
Mr. Blaimberger, Frank L.
Bio
After his Master of Science Degree in Electronics Engineering and Ergonomics at University of Munich (TUM). Before his joining of TUV SUD in June 2019, he worked in several companies such as Siemens, Deutsche Telekom and Fujitsu. His bandwidth of production & manufacturing related experiences as well as his management skills were reached in various and different positions over 24 years - e.g. head of global manufacturing, heading the shopfloor operation and asset technology at 13 factories / sites for data center equipment and semiconductor production.
Frank has implemented technologies, methods and strategies to enable supply chain transformation - implementing Industry 4.0 and Internet of Things (IoT) operations.
He further collaborate and interact with committees, customers and research organizations to settle and deploy smart factory related references, technologies and standards.
At TUV SUD, he is heading the global lead for digitized compliance innovations focusing on operations of digitized assets, industrial software, CyberSecurity, artificial intelligence and digitized compliance management for connected systems.
Orchestrating of skills and technology is Frank’s key to success towards digitized transformation and operation. The Vice President interacts and collaborate with Digital Twin consortiums and AI appliance and infrastructure industry in his daily work at TÜV SÜD.
His goal is to make connected and autonomous operation safe, secure and resilient.
Talk Title
Trustworthiness in the future of automation – AI based decision capabilities for safety and security
Abstract
AI-based decision-making is rapidly becoming a core capability of automated systems in safety- and security-critical domains. As systems grow in complexity and autonomy, trustworthiness is no longer an attribute of individual components but an emergent property of architectures, processes, and ecosystems across the semiconductor lifecycle. This session explores how trustworthiness can be achieved as a foundation for resilient and fail-operational automation.
The talk addresses how the integration of functional safety, cybersecurity, and Safety of the Intended Functionality (SOTIF) enables efficient and robust system behavior. Emphasis is placed on architectural principles, certified components, and continuous digital lifetime monitoring as key enablers of trust across globally distributed supply chains. Recent developments in standards are highlighted, including the forthcoming IEC 61508-2-1, which extends functional safety concepts to semiconductor technologies and clarifies expectations for safety-critical silicon.
The session further discusses predictive maintenance and early detection of degrading semiconductor faults, aligned with ISO/TR 9839:2023, as well as the qualification and controlled use of Agentic AI during design, verification, and production ramp-up. High-integrity System-on-Chip architectures with onboard safety mechanisms are examined in the context of managing dependent and common-cause failures. The role of digital twins in enabling fail-operational behavior and operational resilience is illustrated, along with the combination of Safety Elements out of Context (SEooC) and continuous context monitoring supported by AI and large language models.
This session provides practical insights for engineers, architects, and decision-makers shaping the future of trusted automation.
Mr. Huang, Zheng
Bio
Mr. Zheng Huang holds a Master's degree in Microelectronics from Xidian University and brings over 20 years of experience in full-custom IC design, with a focus on the DFT (Design for Test) area. He began his career at Infineon in 2004 as a DFT engineer, then served as an SoC architect engineer at Intel Communications from 2011. He is currently the Product Director at the EDA department of Semitronix Corporation. His expertise lies in EDA flow solutions and DFT technology development, and the EDA flow and products he has contributed to have been widely adopted across various chip design domains.
Talk Title
Addressing DFT Challenges in Advanced Packaging: Implementation and Application of EDA Solutions
Abstract
Advanced packaging technologies, such as 2.5D/3D integration, chiplet-based designs, and heterogeneous integration, introduce unprecedented complexities in terms of thermal management, signal integrity, power delivery, mechanical stress, and design-for-Test (DFT). Traditional EDA tools and design flows often fall short in addressing these multi-physics and multi-domain challenges within a unified environment.
At Semitronix, we've already developed dft solutions and will demonstract the practical implementation and application of dedicated dft EDA solutions in real-world projects to tackle these hurdles.
Dr. Liu, Wenchao
Bio
Dr. Liu Wenchao, currently serving as Senior Vice President at Primarius and General Manager of Primarius Technologies Guangzhou Branch. He has more than 20 years of experience in technology research and management at international semiconductor companies, also his work areas cover chip manufacturing, IC design, and electronic design automation (EDA). In 2004, he obtained a doctor's degree in microelectronics and solid state electronics from Shanghai Institute of Microsystem and Information Technology; From 2004 to 2005, he served as the Principal Engineer of HHGrace; From 2005 to 2009, he served as the Principal Engineer of IBM Semiconductor R&D Center in the United States; From 2009 to 2018, he also served as Senior Technical Manager in Singapore Chartered Semiconductor and GLOBALFOUNDRIES; From 2018 to 2019, served as the Design Platform Director of Unisoc Technologies.
Talk Title
DTCO: Synergizing Design and Manufacturing, Building Application-Driven EDA Flows
Abstract
As semiconductor innovation becomes increasingly application-driven, stronger synergy between design and manufacturing is essential to EDA development. This presentation discusses the importance of DTCO at advanced nodes, where tight co-optimization across process, device, circuit, and layout is critical to achieving PPA and manufacturability targets. It also highlights the value of process exploration at mature nodes, where application-specific optimization continues to unlock competitive advantages. From TCAD and SPICE simulation to cell generation and characterization, Primarius provides a full-flow methodology that connects process innovation with design enablement. By bridging manufacturing insights and downstream EDA optimization, this end-to-end flow helps accelerate technology development, improve design quality, and support application-driven semiconductor innovation across both advanced and mature process nodes.
Dr. Shen, Chen
Bio
Dr. Shen obtained his doctoral degree in the Department of Electrical and Computer Engineering at the National University of Singapore in 2009. In 2011, he co-founded Suzhou Kejingda Electronics Co., Ltd. During his 20-year entrepreneurial journey, influenced by the spirit of independent and controllable technological innovation passed down through three generations of engineers in his family, he has been firmly committed to the R&D of semiconductor device and process TCAD simulation software. After the company's restructuring in 2021, he serves as the Chairman of Peifeng Tunan Semiconductor (the parent company), continuing to devote himself to the R&D and promotion of EDA software for wafer fabrication.
He has published more than 40 papers in international SCI/EI-indexed journals and conferences, with an h-index of 15. His most highly-cited paper has received over 100 citations, and is among the most-cited literatures in the field of MOSFET reliability in recent years.
Talk Title
Modernizing TCAD: High-Performance Solvers and GPU-Accelerated Architectures for Sub-2nm Technology Development
Abstract
As semiconductor scaling progresses beyond the 2nm node, the aggressive introduction of novel materials, complex processing equipment, and 3D device architectures has created a multidimensional design space. The exponential increase in permutations across the material-process-device-design interface presents a significant computational bottleneck, necessitating advanced simulation frameworks to sustain the pace of innovation. Traditional TCAD methodologies are increasingly strained by the rigorous topographical and physical modeling requirements of the nano-scale regime.
In this presentation, we detail a comprehensive modernization of the TCAD framework designed to address these challenges. We discuss the transition to GPU-accelerated computing architectures, the implementation of novel solvers capable of resolving multi-scale, multi-physics phenomena, and the integration of these tools into a new paradigm for co-optimization. By bridging the gap between fundamental physics and industrial-scale development, this work establishes a scalable foundation for the next generation of semiconductor process technology.
Mr. Yang, Wu
Bio
Wu Yang is the Director of Technical Programs at Siemens EDA. Bringing 27 years of extensive experience in design-for-test (DFT), 2D and 3D IC testing, silicon learning, failure analysis, and reliability, Mr. Yang is a recognized expert in the field. He is a frequent speaker at industry conferences and a regular contributor to technical papers, articles, and public discussions. His current responsibilities have expanded to address new industry challenges in silicon lifecycle management and AI/ML related applications. Mr. Yang has delivered multiple tutorials at prestigious events including ITC, ITC_Asia, ATS, ETS, and VTS. He holds an M.S. degree in Electrical Engineering from Portland State University.
Talk Title
Industrial Trends for Silicon Lifecycle Management
Abstract
TBA
Mr. Yu, Han
Bio
Yuhan works for Huada Empyrean Tech. Corp. from 2010 and he has abundant experience in AMS IC design together with EDA tools development. He participated in the architectural design of Empyrean's full-flow AMS EDA system, as well as the R&D and technical promotion of several digital EDA tools. Currently, he leads Empyrean's initiatives in industry-education integration and ecosystem promotion. Yuhan is also one of the deputy heads of EDA2's AMS and Advanced Packaging workgroup.
Talk Title
Highlights to Full Flow 2.5/3D Chiplets Toolsuit and Development Trend
Abstract
The presentation will describe Empyrean's latest 2.5/3D chiplets full flow EDA architecture including physical implementation, Multi Physics simulation, and verification toolsuites. And also will discuss possible development trends of China domestic EDA in this field.
Dr. Zhao, Yi
Bio
Holding a Ph.D. from the University of Southampton, UK, under the supervision of Royal Society Fellow Professor Bashir Hashimi, he embarked on 2.5D/3D stacked IC design research in 2008 as part of one of the world's earliest pioneering research teams exploring advanced chip architecture methodologies, having collaborated with IMEC for 3D-IC technology validation. With 15 years of dedicated R&D in 3D integrated circuit design, he has published several excellent papers and awarded the VLSI-SOC Best Paper.
Currently serving as Founder and Chief Scientist at Zhuhai Silicon Chip Technology Ltd. , he has been a majority of leading national research initiatives. He directs the team in developing self-proprietary 2.5D/3D Stacked IC EDA tools, enabling critical advancements in the semiconductor industry through backend full-flow EDA tools and solutions.
Talk Title
2.5D/3D Advanced Packaging EDA⁺STCO New Paradigm: architecting & physical implementation, simulation, and testing
Abstract
This report aligns with the cutting-edge trends in system-level modeling and design methodologies, addresses the core design challenges of heterogeneous microsystem integration, and focuses on the pain points and demands of cross-device, cross-process, and cross-hierarchy collaborative design in heterogeneous integration from a system-level modeling perspective. It shares how SiChip Technology, with its independently developed STCO (System Technology Co-Optimization) framework, has redefined advanced packaging design flows and established a new 2.5D/3D EDA+ paradigm.
Based on the 3Sheng Integration Platform for stacked chip design, SiChip has built a full-flow tool chain covering five core modules: 3Sheng Zenith (Architecture Design) – 3Sheng Ranger (Physical Implementation) – 3Sheng Ocean (Multi-die DFT) – 3Sheng Volcano (Co-Simulation) – 3Sheng Stratify (Multi-die Physical Verification)(LVS and DRC). The platform also implements a dual-system approach: "chiplet-interposer-packaging co-design" and "performance-cost-testability co-optimization", enabling efficient full-flow collaboration and global optimization for 2.5D/3D advanced packaging from system planning to mass production.
Combined with industrial cases, the report demonstrates the technological breakthroughs and application value of the STCO-based EDA+ paradigm in advanced packaging heterogeneous integration, and explores how independent 2.5D/3D EDA technologies empower the collaborative development of the advanced packaging industry chain.