Bio.: Giovanni De Micheli is a research scientist in electronics and computer science. He is credited for the invention of the Network on Chip design automation paradigm and for the creation of algorithms and design tools for Electronic Design Automation (EDA). He is Professor and Director of the Integrated Systems Laboratory and Scientific Director of the EcoCloud center at EPFL Lausanne, Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. He was Director of the Electrical Engineering Institute at EPFL from 2008 to 2019 and program leader of the Swiss Federal Nano-Tera.ch program. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).
Prof. De Micheli is a Fellow of ACM, AAAS and IEEE, a member of the Academia Europaea and an International Honorary member of the American Academy of Arts and Sciences. His current research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of ten other books and of over 900 technical publications. His citation h-index is above 100 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B) and STMicroelectronics.
Prof. De Micheli is the recipient of the 2022 ESDA-IEEE/CEDA Phil Kaufman Award, the 2019 ACM/SIGDA Pioneering Achievement Award, and several other awards.
Abstract: Increasingly more stringent requirements for computing systems will outpace our ability to design them using current technologies and methods. Fortunately, we can leverage design automation tools to analyze and synthesize new generations of computing machines, that will depart from their ancestors in terms of realization technology, computing paradigm and interaction with humans. Devices and chips technologies are already evolving into a third dimension. New materials are both enhancing silicon technology and creating viable alternatives. Accelerators of computation leverage the diversity of underlying technology. Yet their efficient design requires new design automation tools.
Within this plurality of possibilities, the computational intractability of even simple design problems will challenge our goals to achieve both high-performance and low-energy computing. Interestingly, many disparate design problems share kernel subproblems, that can be tackled with the help of graph models and discrete mathematics tools. Synthesis is and will be the key enabler for the progress in computing as well as for addressing efficient ways for enhancing privacy and security.
Bio.: Georges G.E. Gielen received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven (KU Leuven), Belgium, in 1986 and 1990, respectively. Currently, he is Full Professor in the MICAS research division at the Department of Electrical Engineering (ESAT) at KU Leuven. From 2013 until 2017 he served as Vice-Rector for the Group of Sciences, Engineering and Technology. In 2018 he was visiting professor at UC Berkeley and Stanford University. From 2020 to 2024 he served as Chair of the Department of Electrical Engineering (ESAT) at KU Leuven.
His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation, including modeling, simulation, optimization and synthesis as well as testing. He has graduated over 55 PhDs so far. He is a frequently invited speaker and serves/served as Distinguished Lecturer of the IEEE Solid-State Circuits Society and the IEEE Circuits and Systems Society. He is coordinator/partner of several academic and industrial research projects in the above fields, including having awarded the ERC Advanced Grant AnalogCreate. He has (co-)authored 14 monograph books and more than 800 publications in edited books, international journals and conference proceedings. He is a 1997 Laureate of the Belgian Royal Academy of Sciences, Literature and Arts in the discipline of Engineering. He is Fellow of the IEEE since 2002, and received the IEEE CAS Mac Van Valkenburg award in 2015, the IEEE CAS Charles Desoer award in 2020, as well as the EDAA Achievement Award in 2021. He is an elected member of the Royal Flemish Academy of Belgium in the class of Technical Sciences, and of the Academia Europaea.
Abstract: Analog/mixed-signal integrated circuits are key in applications where electronics interface with the physical world. But whereas digital circuits are largely synthesized through EDA software, surprisingly, the design of analog circuits in industry is mainly still handcrafted, with long and error-prone design cycles and high development costs. The recent rebirth of AI and machine learning, and the recent rise of generative AI methods, however, create a whole new spectrum of techniques to automate this process. This keynote presentation will explore the high potential of using advanced machine learning (ML) techniques to automatically synthesize and lay out analog integrated circuits. What is hype and what will be feasible? Will we still need analog designers in the future and how will they operate?
Bio.: Dr. Zhou, President of Huawei’s Institute of Strategic Research, joined Huawei in 1997. Dr. Zhou has served as Chief of the Shanghai Research Center, Vice President of the Wireless Network Product Line, President of the Central Hardware Engineering Institute, and President of the European Research Institute etc. In these roles, Dr. Zhou has been responsible for research, standardization, industrialization, and technical cooperation activities of the related business.
Abstract: With the rapid development of digitization, intelligence, and greenization, we are standing at an unprecedented node in the era where society and economy, science and technology, culture and education will undergo tremendous changes in the future. This presents both new opportunities and unprecedented challenges for the ICT field, requiring industry and academia to jointly explore future oriented business visions and technological assumptions, from What to Why and How, to develop efficient, and creative intelligence, and build a better connected and intelligent world with STCO Collaborative Development.
Bio.: Prof. Sung Kyu Lim earned his Ph.D. in Computer Science from UCLA in 2000. Since 2001, he has been a faculty member at the School of Electrical and Computer Engineering at the Georgia Institute of Technology. His research explores the architecture, design, and electronic design automation (EDA) of 2.5D and 3D integrated circuits, contributing to over 400 published papers. He received the Best Paper Awards from the IEEE Transactions on CAD in 2022 and the ACM Design Automation Conference in 2023. He is an IEEE Fellow and served as a program manager at DARPA's Microsystems Technology Office from 2022 to 2024.
Abstract: Multi-chip integration has become standard practice in AI training and is increasingly adopted in edge learning applications. By utilizing 2.5D and 3D IC architectures through multi-chip integration, significant improvements can be made in energy efficiency and latency reduction during data transfers. Central to these advancements is the automation of design and simulation processes for heterogeneous AI chips, where sophisticated algorithms increasingly play a pivotal role, rather than manual human intervention. This transition is powered by advanced electronic design automation (EDA) tools. At Georgia Tech, my research team combines AI-driven and conventional algorithms to enhance EDA capabilities, tailored specifically for the development of state-of-the-art heterogeneous AI chips. In my talk, I will highlight these technological innovations and discuss the prevailing challenges in AI chip design and EDA.
Bio.: Professor Schlichtmann (b. 1964) explores design automation methodologies for complex (digital and analog) electronic circuits and systems. These often consist of billions of components and need to be designed using sophisticated optimization and analysis algorithms. In recent years, his research has increasingly addressed emerging technologies (photonics, microfluidic biochips, neuromorphic architectures).
Professor Schlichtmann studied electrical engineering at TUM and obtained his doctorate for a thesis on computer-aided design, and also pursued a postgraduate business degree during this time. He then worked for Siemens AG and Infineon Technologies AG in a number of technical, managerial and executive positions for about 10 years. In 2003, Professor Schlichtmann was appointed to a professorship at TUM. In addition to his research and teaching activities, he coordinates international study programs in both Munich and Singapore (TUM Asia). He furthermore serves as program director of the TUMCREATE research project in Singapore and is is a member of various advisory boards and of the acatech National Academy of Science and Engineering.
Abstract: Optical networks-on-chip (ONoC) is a next-generation interconnect architecture, e.g. for multiprocessor systems-on-chip (MPSoC). Compared to classic electrical NoCs, ONoC offers much higher bandwidth with wavelength-division multiplexing (WDM), which allows signals to travel through the same medium simultaneously with little interference by modulating them on different wavelengths. Among various types of ONoCs, Wavelength-Routed ONoC (WRONoC) is renowned for being exempt from communication protocols. Specifically, instead of dynamically constructing/destructing signal paths, optical signals are routed passively according to their wavelengths along designated signal paths fixed in the design phase. This way, WRONoC avoids the energy and latency overhead for arbitration and enables all-to-all simultaneous data transmission. This talk presents three design synthesis methodologies and the corresponding research projects conducted at TUM for application-specific WRONoC. In addition, this talk will highlight opportunities for bit-level parallelism maximization and allocation during and after design synthesis and the corresponding challenges that must be addressed, particularly for large-scale networks.
Bio.: Dr. Jinjun Xiong is Empire Innovation Professor with the Department of Computer Science and Engineering at University at Buffalo (UB). He also serves as the Scientific Director for the National AI Institute for Exceptional Education, the AI lead for the IES Center for Early Literacy and Responsible AI, and Director for the SUNY-UB Institute for Artificial Intelligence and Data Science. Prior to that, he was a Senior Researcher and Program Director for AI and Hybrid Clouds Systems at the IBM Thomas J. Watson Research Center. He was the former co-founder and co-director for the IBM-Illinois Center for Cognitive Computing Systems Research (C3SR), the success of which in 5 years has led to the 10-year $200M expansion of the center to the IBM-Illinois Discovery Accelerator Institute. His research interests are on across-stack AI systems research, including AI applications, algorithms, tooling and computer architectures. Many of his research results have been adopted in IBM’s products and tools. He published more than 180 peer-reviewed papers in top AI conferences and systems conferences. His publication won 9 Best Paper Awards and 10 Nominations for Best Paper Awards. He also won top awards from various international competitions, including the championship award for the IEEE GraphChallenge on accelerating sparse neural networks in 2020, and the First Place Awards for the 2019 DAC Systems Design Contest on designing an object detection neural network for edge FPGA and GPU devices, respectively.
Abstract: The increasing power of deep learning-based machine learning (ML) techniques have started to erode many of the traditional equation-based physical modeling techniques, some of which are corner stone technologies for the development of electronic design automation (EDA) as an active area in the past decades. Since the inception of the new area of ML for EDA, there have always been controversies or doubts on the sensibility of such a formulation. Based on the speaker’s years of research experience in both EDA and ML as two separate domains, he will reflect upon his personal learning in these two seemingly different areas, how the controversies may be reconciled, and how a cohesive view on the subject of ML for EDA can be formed. In doing so, the speaker would like to shed some lights on the future of ML for EDA, and what research challenges are ahead of the ML for the EDA research community.
Bio.: Professor Tim Cheng is Vice-President for Research and Development (VPRD) and Chair Professor jointly in the Department of Electronic & Computer Engineering (ECE) and Department of Computer Science & Engineering (CSE) at The Hong Kong University of Science and Technology (HKUST). His current research interests span the fields of AI chip design, electronic design automation (EDA), computer vision, and medical image analysis. He is now directing the InnoHK AI Chip Center for Emerging Smart Systems (ACCESS), a multidisciplinary R&D platform aiming to advance IC design and EDA development in realizing ubiquitous AI applications in society.
Prof. Cheng holds a doctorate from the Univ. of California, Berkeley. Prior to joining HKUST, he was on the faculty at the Univ. of California, Santa Barbara (UCSB) after spending five years at the AT&T Bell Laboratories. At UCSB, he took up various academic leadership roles, including the Founding Director of the Computer Engineering Program, Chair of the ECE Department, and Associate Vice Chancellor for Research. He was Dean of Engineering at HKUST from 2016 to April 2022 before becoming VPRD.
A Fellow of IEEE and the Hong Kong Academy of Engineering Sciences, Prof. Cheng has gained due recognition for his research, including a dozen of best paper awards from IEEE and ACM conferences and journals. On top of receiving the UCSB College of Engineering Outstanding Teaching Faculty Award, the 2020 Pan Wen Yuan Outstanding Research Award, and the 2024 CCF Overseas Outstanding Contribution Award, he was named a Fellow of the School of Engineering at the University of Tokyo.
Abstract: I will give an overview of the multi-faceted technical approaches and recent results at the InnoHK AI Chip Center for Emerging Smart Systems (ACCESS) research center in designing high-performance and energy-efficient edge accelerators for supporting inference of large-scale AI models. Four major trends are driving ACCESS's research agenda: (1) The growth rate of AI model size and complexity is much faster than the performance improvement rate of AI hardware, (2) latency, scalability, privacy, and reliability are driving migration of AI from cloud to edge, (3) AI model inference market is explosive, becoming much bigger than the model training market, and (4) chiplet/3DIC is going mainstream for AI processor implementation. I will showcase our approaches to design of Transformer and LLM accelerators, compute-in-memory macros, an application-algorithm-architecture co-design framework, and an automatically synthesized FPGA-based accelerator for convex optimization solvers.
Bio.: Sachin S. Sapatnekar is the Henle Chair in ECE and Distinguished McKnight University Professor at the University of Minnesota. His research interests include design automation methods for analog and digital circuits, circuit reliability, and algorithms and architectures for machine learning and quantum-inspired computing. He is a Fellow of the IEEE and the ACM.
Abstract: Today's computing models see increasing analog content for two reasons: ever-increasing interaction with an analog real world, and the growing realization that computing on analog substrates can, under certain circumstances, be more efficient than traditional digital computing. For decades, automation has eluded analog design, but with growing design complexity, messy design rules and nontrivial constraints, there has been a renaissance in this field aided partially (but not exclusively) by the emergence of AI. The talk will first overview experience in analog design automation, particularly our experiences with the ALIGN layout automation system, and will overview directions for future research in the field.
Bio.: Vijay Janapa Reddi is an Associate Professor in the John A. Paulson School of Engineering and Applied Sciences at Harvard University. Prior to joining Harvard University, he was an Associate Professor at The University of Texas at Austin. His research interests include computer architecture and runtime systems, specifically in the context of edge and mobile computing systems (smartphones, autonomous vehicles, aerial robots, etc.) to improve their performance, power efficiency, and reliability. Dr. Janapa Reddi is a recipient of multiple honors and technical achievement awards, including the MICRO and HPCA Hall of Fame (2018 and 2019, respectively), the National Academy of Engineering (NAE) Gilbreth Lecturship Honor (2016), IEEE TCCA Young Computer Architect Award (2016), Intel Early Career Award (2013), Google Faculty Research Awards (2012, 2013, 2015, 2017), Best Paper at the 2005 International Symposium on Microarchitecture (MICRO), Best Paper at the 2009 International Symposium on High Performance Computer Architecture (HPCA), and IEEE’s Top Picks in Computer Architecture awards (2006, 2010, 2011, 2016, 2017). Beyond his technical research contributions, Dr. Janapa Reddi is passionate about STEM education at early age. He is responsible for the Austin Independent School District’s “hands-on” computer science (HaCS) program, which teaches 6th- and 7th-grade students programming and the high-level principles governing a computing system using open-source prototyping platforms like Arudinos. He received a BS in computer engineering from Santa Clara University, an MS in electrical and computer engineering from the University of Colorado at Boulder, and a Ph.D. in computer science from Harvard University.
Bio.: Jaijeet Roychowdhury is a Professor of EECS at the University of California at Berkeley. His research interests include machine learning, novel computational paradigms, and the analysis, simulation, verification and design of cyber-physical, electronic, biological, nanoscale and mixed-domain systems. Contributions his group has made include the concept of self-sustaining oscillators for Ising-based and von Neumann computation, novel machine-learning techniques for dynamical systems, theory and techniques for oscillator phase macromodels, injection locking and phase noise, multi-time partial differential equations, techniques for model reduction of time-varying and nonlinear systems, and open-source infrastructures for reproducible research.
Roychowdhury received a Bachelor's degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 1987, and a Ph.D. degree in electrical engineering and computer science from UC Berkeley in 1993. From 1993 to 1995, he was with the Computer-Aided Design (CAD) Laboratory, AT&T Bell Laboratories, Allentown, PA. From 1995 to 2000, he was with the Communication Sciences Research Division, Bell Laboratories, Murray Hill, NJ. From 2000 to 2001, he was with CeLight Inc. (an optical networking startup), Silver Spring, MD. From 2001-2008, he was with the Electrical and Computer Engineering Department and the Digital Technology Center at the University of Minnesota in Minneapolis.
Roychowdhury was cited for Extraordinary Achievement by Bell Laboratories in 1996 for work on MOS homotopy. His student Tianshi Wang and he won the Bell Labs Prize in 2019 for their work on Oscillator Ising Machines. Over the years, he has authored or co-authored seven best papers and a distinguished paper. He has served on technical and administrative committees within several conferences and professional organizations, including ICCAD, DAC, DATE, ASP-DAC and CEDA. Roychowdhury was a co-founder of Berkeley Design Automation, a startup later acquired by Mentor Graphics. He is a Fellow of the IEEE.
Abstract: Modern society has become increasingly reliant on rapid and routine solution of hard discrete optimization problems. Over the past decade, fascinating analog hardware approaches have arisen that combine principles of physics and computer science with optical, electronic and quantum engineering to solve combinatorial optimization problems in new ways---these have come to be known as Ising machines. Such approaches leverage analog dynamics and physics to find good solutions of discrete optimization problems, potentially with advantages over traditional algorithms. Underlying these approaches is the Ising model, a simple but powerful graph formulation with deep historical roots in physics. About eight years ago, we discovered that networks of analog electronic oscillators can solve Ising problems “naturally”.
This talk will cover the principles and practical development of these oscillator Ising machines (OIMs). We will touch upon specialized EDA tools for oscillator based systems and note the role of novel nanodevices. Applied to the MU-MIMO detection problem in modern wireless communications, OIMs yield near-optimal symbol-error rates (SERs), improving over the industrial state of the art by 20x for some scenarios.
More speakers will be updated soon.