Bio.: Luca Benini is a Full Professor of Electronics at the University of Bologna. He also holds a faculty position at the Swiss Federal Institute of Technology, Zurich (ETHZ). In 2009-2012 he has served as Chief Architect in STMicroelectronics for the Platform 2012 project. He received a Ph.D. degree in electrical engineering from Stanford University in 1997.
Dr. Benini has published more than 800 papers in peer-reviewed international journals and conferences, five books and several book chapters. He has been general chair and program chair of the Design Automation and Test in Europe Conference. He has been a member of the technical program committee and organizing committee of several conferences, including the Design Automation Conference, International Symposium on Low Power Design, the Symposium on Hardware-Software Codesign.
He is Associate Editor of the IEEE Transactions on Computer Aided Design of Circuits and Systems and of the ACM Transactions on Embedded Computing Systems .
He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea.

Bio.: Prof Yeo Yee Chia is currently the Deputy Chief Executive (Innovation & Enterprise), A*STAR. He provides strategic leadership and oversight of the Innovation & Enterprise Group and National Platforms. He orchestrates A*STAR's industry approach and priorities to ensure that A*STAR's translational activities achieve significant national impact and outcomes.
Prior to this, he was Assistant Chief Executive (Innovation & Enterprise), where he strengthened A*STAR's industry partnerships and commercialisation efforts. Prof Yeo also held various leadership roles in A*STAR, including Executive Director (IP Management) and Executive Director of the Science & Engineering Research Council (SERC). He leads substantial research efforts at A*STAR's Institute of Microelectronics, working on frontier microelectronic devices and key challenges in semiconductor technology. He plays a significant role in Singapore's Future of Microelectronics initiative to steer next-generation microelectronics strategy.
Prof Yeo is a renowned scholar in academia and a technology leader in the semiconductor industry, with expertise in transistor architecture, device modelling and simulation, materials, tools and processing technologies.
He spent 10 years at Taiwan Semiconductor Manufacturing Company (TSMC). He was Director of Research and Development (R&D) at TSMC where he led organisations spanning research, pathfinding, and development. He co-developed TSMC's industry-leading 7 nm, 5 nm, and 3 nm technologies, which has impacted the world in areas such as high performance computing, artificial intelligence, and consumer electronics.
In academia, he is Professor of Electrical and Computer Engineering, National University of Singapore (NUS), where he was an award-winning, high impact researcher with an outstanding track record of achievements. He published over 700 research papers and is an inventor of 289 US patents. 44 PhD students graduated under his tutelage.
He received his PhD and MS degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, and MEng and BEng degrees in Electrical Engineering from NUS.

Bio.: Subramani (Subi) Kengeri is the Corporate Vice President and General Manager at Applied Materials, leading the Systems-to-Materials group since joining in 2020. He has led world-wide teams in technical and executive roles at Globalfoundries, TSMC, and Texas Instruments. He holds over 50 U.S. patents, and has delivered more than 100 invited talks and interviews.

Bio.: Professor Kiat Seng YEO, (PhD, PPA, PBS, FSAEng, FSNAS, FCAE, FIEEE, FAAET, FAIIA, FAAIA) received his BEng and PhD degrees in EE from Nanyang Technological University (NTU), Singapore. He has 37 years of experience in industry, academia, start-ups and consultancy. Currently, he is Advisor for Global Partnerships (President’s Office) and Director for Innovation and Enterprise (China) at the Singapore University of Technology and Design (SUTD) and Distinguished Professor at Tianjin University. Prof. Yeo is a widely known authority in low-power RF/mm-wave IC design and a recognized expert in CMOS technology. He was the Founding Chairman of the University Research Board, Founding Chairman of the Board of Graduate Studies, Member of the Academic Council, Associate Provost for Research, Founding Associate Provost for Graduate Studies, and Founding Associate Provost for International Relations at SUTD. Before his appointment at SUTD, he was Associate Chair (Research), Head of the Division of Circuits and Systems, and Founding Director of VIRTUS of the School of Electrical and Electronic Engineering at NTU. He has secured over S$70M of research grants as PI, published 14 books (4 Amazon Best Sellers), 7 book chapters, 700+ journal and conference papers, and holds 55 patents (27 US patents). Professor Yeo holds/held key positions in many international conferences as Advisor, General Chair and Technical Chair. He is one of the 7 “double academicians” of the Singapore Academy of Engineering and the Singapore National Academy of Science. He is also a Foreign Fellow of the Canadian Academy of Engineering and Fellows of the ASEAN Academy of Engineering and Technology, the Asia-Pacific Artificial Intelligence Association, the International Artificial Intelligence Industry Alliance, and the IEEE. He received 2 National Day Awards from the President of Singapore in 2009 and 2020 and awarded the Nanyang Alumni Achievement Award by NTU in 2009. He is the principal author of Integrated Circuit Design Research Ranking for Worldwide Universities 2008 and World University Research Rankings (WURR) 2020. Professor Yeo was recognized among the Top 2% Scientists Worldwide by Stanford University from 2020 to 2025, World’s AI Top Scientist by the International Artificial Intelligence Industry Alliance in 2023, and Top Scholar by ScholarGPS from 2023 to 2025.

Bio.: Don Chan is the Vice President of R&D at Cadence. He leads a global team responsible for advanced nodes development and support of the leading foundry in the world.
Don joined Cadence in Nov 2018. Prior to his current role, he held several leadership positions at Synopsys since 1993 where he led a global organization of Applications and R&D engineers responsible for providing RTL-GDS solutions for advanced IC Design. Don also teaches logic design classes at SCU in Silicon Valley. He began his engineering career at Spectrum Software in 1986 and joined Fujitsu Microelectronics in 1988 as an ASIC Design Engineer.

Bio.: Keshab K. Parhi received the B.Tech. (Honors) degree from the Indian Institute of Technology, Kharagpur (India) in 1982 in Electrical Engineering, the M.S. degree from the University of Pennsylvania in 1984 in Electrical and System Engineering, and the Ph.D. degree from the University of California, Berkeley in 1988 in Electrical Engineering and Computer Sciences.
Dr. Parhi has been with the Department of Electrical & Computer Engineering at the University of Minnesota, Minneapolis, since 1988, where he was an Assistant Professor from Oct. 1988-June 1992, Associate Professor from July 1992-June 1995, and has been a Professor since July 1995. Since July 2022, he holds the inaugural Erwin A. Kelen Chair in Electrical Engineering. Since 2000, He has held the permanent title of "Distinguished McKnight University Professor" awarded by the Graduate School of the University. During July 1997 - June 2022, he held the title of "Edgar F. Johnson Professor of Electronic Communication." During July 2008 - August 2011, he served as the Director of Graduate Studies of the Electrical Engineering program. He has held short term positions in several industries such as IBM T.J. Watson Research Center (Yorktown Heights, NY), AT&T Bell Laboratories (Holmdel, NJ), NEC Corporation (Miyamae-Ku, Kawasaki, Japan), where he was a National Science Foundation Japan Fellow, Broadcom Corp., Irvine, CA, and Medtronic Corp., Minneapolis, MN. He has been a visiting Professor at Delft University (The Netherlands), Lund University (Sweden), Fudan University (Shanghai, China), and Stanford University. During 2005-2012, he served as Founder and Chief Scientist of Leanics Corp.
Dr. Parhi is widely recognized for his work on high-level transformations of iterative data-flow computations, for developing a formal theory of computing for design of digital signal processing systems, and for contributions to multi-gigabit transceivers for wired systems such as ethernet on copper and fiber and for backplanes, and for wireless communications systems. These high-speed and low-power transceiver integrated circuit chips form the backbone of the internet. His research addresses VLSI architecture design and implementation of signal processing, artificial intelligence and machine learning, communications, biomedical systems, error control coders and cryptography architectures, high-speed transceivers, stochastic computing, secure computing, and molecular/DNA computing. He is also working on intelligent classification of biomedical signals and images, for applications such as seizure prediction and detection, schizophrenia classification, biomarkers for mental disorders, brain connectivity, and screening of fundus and optical coherence tomography (OCT) images for ophthalmic abnormalities. He has published over 745 papers (out of which 16 have won best paper or best student paper awards), is inventor or coinventor of 36 issued US Patents, has authored the text book VLSI Digital Signal Processing Systems: Design and Implementation (Wiley, 1999), and is the co-editor (with Takao Nishitani) of the reference book Digital Signal Processing for Multimedia Systems (CRC Press, March 1999). He has coauthored the research monographs Pipelined Adaptive Digital Filters (with Naresh Shanbhag, 1994), Digit-Serial Computation (with Richard Hartley, 1995), and Pipelined Lattice and Wave Digital Recursive Filters (with Jin-Gyun Chung, 1996), all published by Springer. He has advised 52 graduated Ph.D. students, 65+ MSECE Projects/Theses students, and has supervised 22 Pre- and Post-doctoral visitors.
Dr. Parhi is the recipient of numerous awards including the 2017 Mac Van Valkenburg award from the IEEE Circuits and Systems Society, 2013 Distinguished Alumnus Award from IIT, Kharagpur, India, 2013 Graduate/Professional Teaching Award from the University of Minnesota, 2012 Charles A. Desoer Technical Achievement award from the IEEE Circuits and Systems Society, the 2004 F. E. Terman award from the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W. R. G. Baker prize paper award, and a Golden Jubilee medal from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — PART I and PART II, VLSI Systems, Signal Processing, Signal Processing Letters,and Signal Processing Magazine, and served as the Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — PART I (2004-2005 term), and currently serves as the Editor-in-Chief of the IEEE Circuits and Systems Magazine. He also serves on the Editorial Board of the Springer Journal of Signal Processing Systems (JSPS). He has served on technical program committees of IEEE or ACM Conferences such as ASAP, ICASSP, ISCAS, HOST, Asilomar Conf. Signals, Systems and Computers, Computer Arithmetic Symp., Great Lakes Symp. on VLSI, workshop on VLSI Signal Processing, SiPS, Workshop on VLSI in Communications, and of ASP-DAC, IECS and IWISP conferences. He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996-1998, and during 2019-21. He served as an elected member of the Board of Governors of the IEEE Circuits and Systems society from 2005 to 2007. He is a Fellow of IEEE (1996), tthe Association for Computing Machinery (ACM) (2020), the American Institute for Medical and Biological Engineering (AIMBE) (2022), he American Association for the Advancement of Science (AAAS) (2017), and the National Academy of Inventors (NAI) (2020).

Bio.: Prof. Krishnendu Chakrabarty is the Fulton Professor of Microelectronics in the School of Electrical, Computer and Energy Engineering at Arizona State University (ASU). He is also the CTO of the SWAP Hub for the Department of War Microelectronics Commons (https://microelectronics.asu.edu/southwest-advanced-prototyping-hub/), and Director of the ASU Center for Semiconductor Microelectronics (ACME, http://acme.asu.edu). Before moving to ASU, he was the John Cocke Distinguished Professor and Chair of Electrical and Computer Engineering at Duke University. Prof. Chakrabarty is a recipient of the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award, the IEEE Transactions on VLSI Systems Prize Paper Award, the ACM Transactions on Design Automation of Electronic Systems Best Paper Award, and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award, the IEEE Circuits and Systems (CAS) Society Charles A. Desoer Technical Achievement Award, the IEEE CAS Society Vitold Belevitch Award, the Semiconductor Research Corporation (SRC) Technical Excellence Award, the SRC Aristotle Award, the SRC Innovation Award, the IEEE-HKN Asad M. Madni Outstanding Technical Achievement and Excellence Award, and the IEEE Test Technology Technical Council Bob Madge Innovation Award. He is a Research Ambassador of the University of Bremen (Germany) and he was a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany during 2016-2019. He is a 2018 recipient of the Japan Society for the Promotion of Science (JSPS) Invitational Fellowship in the “Short Term S: Nobel Prize Level” category. He is also a recipient of the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur. Prof. Chakrabarty is a Fellow of ACM, IEEE, and AAAS, and a Golden Core Member of the IEEE Computer Society. He is a Fellow of the National Academy of Inventors.

Bio.: Massimo Alioto is Provost's Chair Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, the Integrated Circuits and Embedded Systems area, and the FD-fAbrICS center on intelligent&connected systems. Previously, he held positions at the University of Siena, Intel Labs - CRL (2013), University of Michigan - Ann Arbor (2011-2012), University of California - Berkeley (2009-2011), EPFL - Lausanne.
He is (co)author of 400 publications on journals and conference proceedings, and four books with Springer (with two more coming). His primary research interests include ultra-low power and self-powered systems, green computing, circuits for machine intelligence, hardware security, and emerging technologies.
He was the Editor in Chief of the IEEE Transactions on VLSI Systems and Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He was the Chair of the Distinguished Lecturer Program for the IEEE CAS Society, and was a Distinguished Lecturer for the SSC and CAS Society. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012). He served as Guest Editor of numerous journal special issues (JSSC, TCAS-I, JETCAS…), Technical Program Chair of several IEEE conferences (ISCAS, SOCC, PRIME, ICECS), and TPC member (ISSCC, ASSCC). His research group contribution has been recognized through various best paper awards (e.g., ISSCC), and in the ten technological highlights of the TSMC annual report, among the others. Prof. Alioto is an IEEE Fellow.

Bio.: Atsushi TAKAHASHI received his B.E., M.E., and D.E. degrees in electrical and electronic engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1989, 1991, and 1996, respectively. He had been with the Tokyo Tech as a Research Associate from 1991 to 1997, and as an Associate Professor from 1997 to 2009 and from 2012 to 2015, and as a Professor from 2015. He had been with the Osaka University as an Associate Professor from 2009 to 2012. He is currently a Professor with Department of Information and Communications Engineering, School of Engineering, Tokyo Institute of Technology. He served as the TPC Chair of ASP-DAC 2018, the General Chair of ASP-DAC 2023, and he is currently a vice chair of Steering Committee of ASP-DAC. He also served as the chair/co-chair/TPC member of top conferences such as ASP-DAC, ISPD, ICCAD, DATE and VLSI-DAT. He was a Board of Governors of IEEE CASS from 2015 to 2019, the chair of All Japan Joint Chapter of IEEE CEDA from 2015 to 2016, the chair of Japan Joint Chapter of IEEE CASS from 2020 to 2021, and the President of Engineering Sciences Society of IEICE in 2021. His research interests include in VLSI layout design and combinational algorithms. He is a fellow of IEICE, and a senior member of IEEE and IPSJ, and a member of ACM.

Bio.: Hans-Joachim Wunderlich is Professor Emeritus of the University Stuttgart and a Life Fellow of IEEE. He received the diploma degree in mathematics from the University of Freiburg, Germany, in 1981 and the Dr. rer. nat. (Ph.D. degree) from the University of Karlsruhe in 1986. Since 1991, he has been a full professor. From 2002 to 2018, he was the director of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart, Germany. He has been associate editor of various international journals and organizer of a variety of IEEE conferences on design, test and fault tolerance of electronic systems. He has published 15 books and book chapters and around 300 reviewed scientific papers in journals and conferences. His research interests include test, reliability, fault tolerance and design automation of microelectronic systems.