EDA² | ISEDA 2025

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Welcome to ISEDA 2025

HONG KONG MAY 9-12, 2025

Sponsored by IEEE and ACM, and jointly organized by EDA² and the EDA Committee of CIE, the ISEDA (International Symposium of EDA) is an annual premier forum dedicated to VLSI design automation. The symposium aims at exploring the new challenges, presenting leading-edge technologies and providing EDA community with opportunities of predicting future directions in EDA research areas. ISEDA covers the full range of EDA topics from device and circuit levels up to system level, from analog to digital designs as well as manufacturing. The format of meeting intends to cultivate productive and novel interchangeable ideas among EDA researcher and developers. Academic and industrial EDA related professionals who are interested in EDA's theoretical and practical research are all welcomed to contribute to ISEDA.

Keynote Speakers

More speakers will be updated soon...

Prof. Giovanni De Micheli

École polytechnique fédérale de Lausanne (EPFL)

Prof. Jaijeet Roychowdhury

University of California, Berkeley

Prof. Sung-Kyu Lim

Georgia Institute of Technology (Gatech)

Prof. Ulf Schlichtmann

Technical University of Munich (TUM)

Prof. Jinjun Xiong

University of Buffalo

Prof. Tim Kwang-Ting CHENG

The Hong Kong University of Science and Technology

Prof. Sachin Sapatnekar

University of Minnesota

About the Tutorials

Hans-Joachim Wunderlich

Professor Emeritus at the University of Stuttgart

Test and Health Monitoring under Approximations and Variations

Bio: Hans-Joachim Wunderlich is Professor Emeritus of the University Stuttgart and a Life Fellow of IEEE. He received the diploma degree in mathematics from the University of Freiburg, Germany, in 1981 and the Dr. rer. nat. (Ph.D. degree) from the University of Karlsruhe in 1986. Since 1991, he has been a full professor. From 2002 to 2018, he was the director of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart, Germany. He has been associate editor of various international journals and organizer of a variety of IEEE conferences on design, test and fault tolerance of electronic systems. He has published 15 books and book chapters and around 300 reviewed scientific papers in journals and conferences. His research interests include test, reliability, fault tolerance and design automation of microelectronic systems.

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iseda2025-tutorial-Hans-Joachim_Wunderlich

Call for Papers

Original papers in, but not limited to, the following areas are invited:

1.1 HW/SW co-design, co-simulation and co-verification
1.2 System-level design exploration, synthesis, and optimization
1.3 System-level formal verification
1.4 System-level modeling, simulation and validation
1.5 Networks-on-chip and NoC-based system design
1.6 Constructing Hardware in Scala Embedded Language

System-Level Modeling and Design Methodology

2.1 Storage system and memory architecture
2.2 On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc.
2.3 Memory/storage hierarchies and management for emerging memory technologies
2.4 Near-memory and in-memory computing

Memory Architecture and Near/In Memory Computing

3.1 Analog/mixed-signal/RF synthesis
3.2 Analog layout, verification, and simulation techniques
3.3 High-frequency electromagnetic simulation of circuit
3.4 Mixed-signal design consideration

Analog-Mixed Signal Design Automation

4.1 Digital Simulation / Emulation
4.2 High-Level Synthesis
4.3 Logic Synthesis
4.4 Synthesis for Approximate Computing

High-Level, Behavioral, and Logic Synthesis and Optimization

5.1 Deterministic/statistical timing analysis and optimization
5.2 Process technology modeling for timing analysis
5.3 Power modeling, analysis and simulation
5.4 Low-power design and optimization at circuit and system levels
5.5 Thermal aware design and dynamic thermal management
5.6 Energy harvesting and battery management

Analysis and Optimization for Power and Timing

6.1 Floorplanning, partitioning, placement and routing optimization
6.2 Interconnect planning and synthesis
6.3 Clock network synthesis
6.4 Physical design of 3D/2. 5D IC and package ( e.g., TSV, interposer, monolithic)
6.5 Post layout and post-silicon optimization
6.6 Layout Verification

Physical Implementation

7.1 RTL and gate-leveling modeling, simulation, and verification
7.2 Circuit-level formal verification
7.3 ATPG, BIST and DFT
7.4 System test and 3D IC test, online test and fault tolerance
7.5 Memory test and repair

Testing, Validation, Simulation, and Verification

8.1 Design-technology co-optimization (DTCO)
8.2 Standard and custom cell design and optimization
8.3 Reticle enhancement, lithography-related design optimizations and design rule checking
8.4 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
8.5 Device-, gate, and circuit-level techniques for reliability analysis and optimization (e.g., soft error, aging, etc.)
8.6 Post-Layout optimizations

Design for Manufacturability and Reliability

9.1 Extraction, TSV, and package modeling
9.2 Chiplet Design and Design tools
9.3 Chip Level Thermal Simulation
9.4 Packaging Stress Analysis
9.5 Multi-Physics Simulation
9.6 Signal/Power integrity, EM modeling and analysis

Packaging & Multi-Physics Simulation

10.1 Device Compact Modeling
10.2 Process Design Kit
10.3 Semiconductor Process & Device Simulation
10.4 Cell Library Design, Characterization and Verification
10.5 New transistor/device and process technology: spintronic, phase-change, single-electron, 2D materials, etc.

Technology & Modeling

11.1 Biomedical, biochip, nanotechnology, MEMS
11.2 Design automation for 3D ICs and heterogeneous integration
11.3 Design automation for quantum computing
11.4 Design automation for silicon photonics
11.5 Design automation for compound semiconductors verification

Emerging Technologies and Applications

12.1 Artificial Intelligence for EDA
12.2 Cloud / Parallel Computing for EDA
12.3 Open Source EDA
12.4 EDA Database
12.5 EDA Standardization

AI & Open Source EDA

Important Dates

Deadline for Regular Paper Submission:
~~February 10, 2025~~

February 28, 2025 (Extended)
Notification of Acceptance:
~~March 10, 2025~~

March 25, 2025 (Extended)
Deadline for Final Version:
~~March 31, 2025~~

April 10, 2025 (Extended)
Deadline for Invited Talks, Extended Abstracts, Tutorials, Special Sessions, Industry Sessions:
March 15, 2025

Important News

20Dec. 2024

ISEDA 2025

The conference proceedings of ISEDA 2024 have been successfully indexed by EI Compendex and Scopus. We are excited to announce that ISEDA 2025 will take place at the Hong Kong Disneyland Hotel from May 9 to May 12, 2025. Welcome to submit your papers. Click to submit your paper now!

14May. 2024

ISEDA 2024

ISEDA 2024 was successfully held in Xi'an from May 10 to May 13, 2024. Click to learn more!

IEEE/CEDA, ACM/SIGDA

Department of Information Science, National Natural Science Foundation of China (NSFC)

Chinese Institute of Electronics (CIE)

Steering Committee, Major Plan of "Fundamental Research on Post-Moore Novel Devices"

EDA Ecosystem Development Accelerator (EDA²)

EDA Committee of CIE

The Chinese University of Hong Kong

Peking University

Southeast University

Tsinghua University

Xidian University