ECOS Studio: Building an Open Ecosystem for Silicon Design and Education

Abstract: This tutorial introduces an emerging open silicon design ecosystem that aims to significantly lower the barriers to custom chip development for researchers, engineers, and students. While open hardware initiatives have expanded rapidly in recent years, practical adoption is often limited by fragmented open-source EDA tools, limited access to manufacturable process technologies, and the complexity of the full RTL-to-chip design flow. Addressing these challenges requires not only individual tools or IP blocks, but an integrated ecosystem that connects design automation, reusable IP, fabrication access, and education.

The tutorial presents a holistic approach to open chip design centered on ECOS Studio, an integrated RTL-to-chip framework that combines open-source EDA tools, an open IP library, and an open-source manufacturable process design kit into a unified workflow. In addition, the tutorial will demonstrate how the toolchain can be used in practice to implement a chip starting from RTL, illustrating the key steps of the design flow and the practical considerations involved in bringing a design to silicon. The goal is to make silicon development more accessible and agile, enabling users to move from RTL to fabricated chips with substantially reduced effort.

Beyond the technical infrastructure, the tutorial also discusses ecosystem-level initiatives that promote large-scale participation in silicon design, including education-oriented chip design programs and SoC development with open, reusable IP components. These efforts illustrate how open ecosystems can accelerate innovation, expand access to silicon prototyping, and foster a broader community around open hardware design.

Tentative Schedule:

1. Opening (~5 mins)
2. Talk 1 (~30 mins)
3. Talk 2 (~30 mins)
4. Talk 3 (~20 mins)
5. Showcasing tape-out; Q&A (~ 10 mins)

AI for EDA Feedback Loops: Leveraging Manufacturing Data to Evolve PDKs, Models, and Design Rules

Abstract: Modern Electronics Design Automation (EDA) flows rely heavily on Process Design Kits (PDKs), compact models, and design rules that abstract complex silicon behavior into usable forms for simulation and verification. However, these abstractions are often treated as static, even as real manufacturing processes exhibit variability, drift, and previously unseen failure modes. This tutorial introduces a paradigm shift where AI and machine learning are used to close the loop between fabricated silicon and design environments. By leveraging large-scale manufacturing data—such as electrical test results, in-line metrology, defect maps, and process time-series—participants will learn how data-driven models can uncover hidden patterns, quantify variability, and systematically refine the parameters and assumptions embedded within PDKs and design rules.
The tutorial will present practical AI workflows that translate manufacturing insights into actionable updates for EDA, including variability-aware compact model calibration and data-driven design rule refinement. Through case studies inspired by real semiconductor datasets, attendees will see how techniques such as regression, classification, and anomaly detection can be repurposed to inform SPICE model updates, identify layout hotspots, and enable continuous learning in design flows. By the end of the session, participants will gain a clear understanding of how AI can transform EDA from a static, assumption-driven process into a dynamic, feedback-enabled ecosystem grounded in silicon reality.

CMOS Technology and Its Application to Design Multi-Standard RF/mm-Wave Low-Noise Amplifiers

Abstract: Big challenges lie ahead for chip designers when they choose to develop ICs using silicon technology for low power and high data rate applications. This is because silicon technology suffers from undesirable energy dissipation due to its lossy substrate and high resistive wiring loss at RF/mm-Wave frequencies. Nonetheless, silicon remains the most suitable material satisfying the demands of a rapidly growing semiconductor market through low fabrication cost and ease of achieving system-on-chip or system-in-package integration.
The transistor promises to revolutionize electronics; indeed, it has become an integral and essential part of our life. A key aspect of chip design is the characterization and modelling of passive devices. For example, physical design parameter optimization of on-chip inductors is performed to achieve similar inductance values as an experimental control to investigate how its core diameter, conductor spacing, and width affect their peak quality factors. The use of these optimized inductors is demonstrated to enhance the circuit characteristics of a giga-hertz amplifier.
While metallization in the form of inductors are “friends” that store magnetic energy, as interconnects, they are however, “foes” to RF/mm-Wave IC designers. Without considering these parasitics from interconnects in the design phase, fabricated RF/mm-Wave circuits suffer power loss and shifts in circuit operating frequencies. A new figure of merit, intrinsic factor, IF, has been proposed in this work to provide a convenient quantitative indication as to how interconnects affect the performance of RF/mm-Wave ICs.
One of the key challenges in realizing multi-standard communications is how to design low-noise amplifiers (LNAs) that can operate in different frequency bands with less inductor number and small inductor value. Based on the above-mentioned concerns, the investigation on the designs of dual-band LNAs, as well as a modified architecture used for input matching in CMOS LNAs to make the circuit more compact, is presented. The proposed design approach can achieve compact and fully integrated LNAs for multi-standard communications.
This tutorial covers 3 topics: 1) The Past, Present and Future of Semiconductors, Global Semiconductor Market, Early Computers, RF Revolution and CMOS Future Directions; 2) Characterization and Modeling of Spiral Inductors, Circuit Verification of Inductor Design Methodology, Characterization and Modeling RF Interconnects, and RF Interconnects Model Verification; and 3) Review of LNA Designs, A New Input Architecture for CMOS LNAs, A Narrow-Band LNA Design Using the New Input Architecture, and Dual-Band LNA Design Using the New Input Architecture.
This tutorial is aimed at students, instructors, IC designers, engineers, and researchers working in CMOS technology and RFIC design. It will enhance their knowledge of the subject, and inspire them to pursue the subject further. The techniques and methodologies presented in this tutorial can help IC designers to reduce the design cycle time and enable them to achieve first pass silicon success.

Design methodologies for intelligent & perceptive hardware security - From circuits to machine learning algorithms

Abstract: The rapidly expanding attack surface of connected devices and the decreasing cost of hardware security attacks now demand ubiquitous deployment of security countermeasures down to edge silicon systems. In this tutorial, the on-going and prospective evolution of design methodologies for on-chip hardware security is presented through an original macro-trend analysis, based on a database that is shared with the attendees as part of the tutorial toolkit. The tutorial covers recent and promising directions to protect confidential information/data in intelligent sensors (e.g., on-chip AI model) from network down to physical level. As emerging security trend towards more self-reliant edge devices, on-chip intelligent sensors (intelligent & perceptive) with built-in AI to autonomously detect and respond to attacks are discussed.

Design methodologies for on-chip sensing, attack detection, actuation and attack counteraction are introduced for key classes of attacks from non-invasive to invasive. A wide range of methodologies and architectures of on-chip frontends and actuators is introduced to inexpensively monitor the chip environment continuously, gaining physical context awareness and capturing physical anomalies. This trend is progressively fusing with relentless advances in inexpensive on-chip (AI) intelligence, which can oversee physical signals and events to orchestrate the on-chip security ecosystem.

The road towards ubiquitous intelligent & perceptive hardware security countermeasures is illustrated through the analysis of recent silicon demonstrations with unprecedented capabilities to perceive security events inexpensively, and react to them intelligently, all the time (always-on). The new concept of hardware patching is also discussed where circuit flexibility is introduced to make silicon chips able to evolve over time, and counteract newly discovered vulnerabilities through (machine) learning-based physical protection mechanisms.

OUTLINE/SCHEDULE:

1. HW security challenges towards trillions of connected devices
   • Edge attack surface extending exponentially
   • Ubiquitous HW security
   • HW security challenges towards the trillions
2. Immersed-in-logic and in-memory security primitives (fully-digital fully-automated design)
   • Root of trust and chain of trust
   • On-chip intrinsic root of trust
   • State of the art review through the “hardware security database”
   • Primitive architectures for ubiquitous security
3. On-chip sensorization for physical attack detection (fully-digital fully-automated design)
   • Side-channel attack detection
   • Laser Voltage Probing (LVP) attacks and on-chip detection
4. Machine learning-based counteraction of side-channel attacks: hardware patching and self-learning
   • HW patchability via ML-based counteraction
   • Neural net reverse engineering counteraction under voltage scaling
   • Online learning-based countermeasure against power analysis attacks
5. Conclusions

Design of Energy-Constrained AI Accelerators for Edge Computing

Abstract:
This tutorial presents a comprehensive overview of the design methodologies and emerging techniques for energy-constrained AI accelerators targeting edge computing applications. As artificial intelligence continues to move from cloud-centric platforms to resource-limited edge devices, stringent constraints on energy consumption, area, and latency necessitate fundamentally new approaches to both hardware design and algorithm development. This tutorial is organized into two complementary parts: (1) computing-in-memory (CiM) architectures for energy-efficient AI acceleration, and (2) hardware–algorithm co-design strategies for embodied AI systems.
The first part of the tutorial focuses on computing-in-memory as a promising paradigm to overcome the energy bottleneck associated with conventional von Neumann architectures. By integrating memory and computation within the same physical location, CiM significantly reduces data movement, which is a dominant contributor to energy consumption in modern AI workloads. The tutorial will cover key CiM design principles, including SRAM- and emerging memory-based implementations, analog versus digital CiM trade-offs, and circuit-level challenges such as nonlinearity, device variation, and limited precision. Practical design techniques for improving energy efficiency and robustness—such as variation-aware analog-to-digital conversion, calibration methods, and quantization-aware design—will be discussed.
The second part of the tutorial addresses hardware–algorithm co-design for embodied AI, where intelligent agents interact with dynamic physical environments under tight energy and latency constraints. Unlike traditional AI workloads, embodied AI requires continuous perception, decision-making, and closed-loop control, often in real time and directly on edge devices. This makes it essential to jointly optimize algorithms, architectures, and hardware implementations in order to achieve efficient end-to-end system performance. This part will highlight representative co-design methodologies and case studies spanning multiple embodied sensing modalities and application scenarios. Topics will include: (1) hardware–algorithm co-optimization for real-time 2D/3D vision-based gesture recognition chips for human–computer interaction; (2) the design of low-latency vision chips for fast-moving object detection and tracking based on both frame-based CMOS image sensors and event-driven dynamic vision sensors; (3) event-triggered tactile sensing and processing systems for low-power, scalable robotic e-skins; and (4) an energy-efficient self-organizing map (SOM) processor based on computing-in-memory (CiM) architecture for continuous on-device adaptation to new knowledge. Through these examples, the tutorial will illustrate how embodied AI workloads introduce unique requirements in sensing, data representation, temporal processing, adaptability, and hardware efficiency, and how co-design across the algorithm, architecture, and circuit levels can address these challenges

Sub-THz Circuits and Systems for Radar Transceivers

Abstract: With sub-THz frequencies becoming increasingly important for high-resolution radar, imaging, and emerging sensing platforms, there is a timely need for a tutorial dedicated specifically to radar transceiver design beyond conventional mm-wave operation. This tutorial introduces the fundamentals of sub-THz circuits and systems for radar transceivers, with emphasis on wideband FMCW/chirp generation, low-phase-noise LO and frequency synthesis, transmitter and receiver design, phased-array beamforming, beam steering, calibration, and chip-package-antenna co-design. Particular attention will be given to the circuit and system bottlenecks that dominate above 100GHz, including limited device gain, output-power constraints, receiver noise, phase-noise accumulation, broadband signal distribution, on-chip/AiP consideration with loss, and packaging-aware integration. By focusing on radar-oriented sub-THz transceivers and their end-to-end system realization, this tutorial is positioned distinctly from recent ISSCC tutorials that emphasized broader wireless communication topics or general mm-wave design practices, and instead addresses the specific architectural and implementation challenges of fully integrated sub-THz radar systems