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Test and Health Monitoring under Approximations and Variations
Abstract: Process and dynamic variations including voltage and temperature fluctuations, crosstalk interaction or aging effects complicate distinguishing between defects, reliability threats, and benign behavior. New compute paradigms like approximate computing aggravate the problem since they may hide malicious reliability threats. This tutorial introduces into the most recent techniques for offline and online test and health monitoring under variations and presents simulation and test generation techniques to overcome the multi-dimensional variation space. Case studies show, how error rate monitoring under dynamic voltage/frequency scaling and approximate computing and communication lead to improvements of performance, power consumption and reliability at the same time.
Tutorial Speaker
Hans-Joachim Wunderlich
Bio: Hans-Joachim Wunderlich is Professor Emeritus of the University Stuttgart and a Life Fellow of IEEE. He received the diploma degree in mathematics from the University of Freiburg, Germany, in 1981 and the Dr. rer. nat. (Ph.D. degree) from the University of Karlsruhe in 1986. Since 1991, he has been a full professor. From 2002 to 2018, he was the director of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart, Germany. He has been associate editor of various international journals and organizer of a variety of IEEE conferences on design, test and fault tolerance of electronic systems. He has published 15 books and book chapters and around 300 reviewed scientific papers in journals and conferences. His research interests include test, reliability, fault tolerance and design automation of microelectronic systems.
Advanced Open-Source FPGA HLS and Physical Implementation Tools
Abstract: Computer-Aided Design (CAD) of Field-Programmable Gate Arrays (FPGAs) has been a hot topic in the rapid advancement and adoption of FPGA technology over the past decades. FPGA CAD flow consists of three major steps: high-level synthesis (HLS) and logic synthesis, physical implementation, and bitstream generation.
FPGA CAD flow has several unique characteristics different from conventional application specific integrated circuit (ASIC) design flows due to the high heterogeneity of FPGA architectures, for example, instance packing, resource heterogeneity and large routing scale. Thus, most of the existing works highly rely on FPGA vendors’ CAD tools to obtain indirect feedback and tightly bind to vendors’ architectures, limiting the flexibility of algorithms and the ability to adapt to new FPGA architectures.
In this tutorial, we have planned three talks to address different aspects of open-source FPGA CAD tools to tackle those challenges. Our first session will provide OpenPARF, an open-source placement and routing framework for large-scale heterogeneous FPGAs with deep learning toolkits. Our second talk will introduce LEAPS, a comprehensive, systematic, and adaptable multi-die FPGA placement algorithm for SLL minimization. Our third session will delve into novel power modeling and optimization strategies tailored for HLS, and introduce power-efficient design methodologies on modern heterogeneous reconfigurable platform, Versal ACAP.
Tutorial Speakers
Zhi-Xiong Di
Zhi-Xiong Di, School of Integrated Circuits, Southwest Jiaotong University, Associate Professor, Doctoral Supervisor. His research focuses on physical implementation algorithms, FPGA accelerator design. He has published papers in IEEE TCAS-I, IEEE TCAS-II, IEEE TCAD, DAC, and others. He has served as a Guest Editor for IEEE TCAS-II, and has guided students to win first prizes multiple times in the EDA Elite Challenge.
Zhe Lin
Zhe Lin is an Assistant Professor at the School of Integrated Circuits, Sun Yat-sen University (SYSU). Before joining SYSU, he held research positions at Peng Cheng Laboratory, where he served as an Associate Research Fellow from January to March 2023 and as an Assistant Research Fellow from March 2020 to December 2021. He earned his Ph.D. in Electronic and Computer Engineering from the Hong Kong University of Science and Technology (HKUST) in 2020. Dr. Lin was awarded the Huawei Young Academic Talent Funding and Oversea High-Caliber Personnel in Shenzhen. As the first author or corresponding author, his paper has been nominated for best paper awards at ICCD 2024, DATE 2022, and FCCM 2019. He served as a technical program committee member for several leading conferences, such as DAC 2025, DATE 2025, ASP-DAC 2025, and FPT 2024.
Jiarui Wang
Jiarui Wang is a fourth-year Ph.D. student at the School of Computer Science, Peking University, advised by Prof. Yibo Lin. He received the B.S. degree in Computer Science and Technology from Peking University in 2021. His research focuses are FPGA routing and multi-FPGA system design flows. He has published 11 papers in DAC, ASP-DAC, TCAD and others. He has served as a reviewer for TCAD and TODAES. He is the co-author of OpenPARF, a high-performance open-source FPGA placement and routing framework. He won the first prize of EDA Elite Challenge 2022.
Jing Mai
Jing Mai is a fourth-year Ph.D. student at the School of Computer Science, Peking University, under the supervision of assistant professor Yibo Lin. He received his bachelor’s degree from the School of Information Science and Technology, Peking University in 2021. His research interests include machine learning-assisted electronic design automation, machine learning systems and high performance computing. He has published 13 papers in prestigious venues including DAC, ICCAD, ASP-DAC, ISPD, TCAD, TCAS-I, and TPDS. He is the core author of OpenPARF, a high-performance open-source FPGA placement and routing framework. He led a team to achieve second place in the MLCAD 2023 large-scale FPGA macro placement competition. He received the Best Paper Award at ISEDA 2024 and won First Place in the ACM SIGDA CADathlon Contest 2024.
VLSI Physical Design, From 2D to 3D
Abstract: VLSI physical design plays a pivotal role in the semiconductor industry. It serves as the crucial bridge between the conceptual design of integrated circuits and their actual fabrication, directly influencing the PPA (power, performance, area) and cost of the final chips. With the relentless pursuit of PPA in modern electronics, the significance of accurate and efficient physical design has become even more pronounced.
In recent years, there has been a remarkable evolution from traditional 2D ICs to 3D ICs. 2D ICs have long been the cornerstone of the semiconductor field, but as the limitations of planar scaling become increasingly evident, 3D IC technology has emerged as a promising alternative. 3D ICs stack multiple layers of active devices vertically, enabling shorter interconnect lengths, higher bandwidth, and better integration of heterogeneous technologies. This transition not only provides new opportunities for innovation, but also poses a series of new challenges in the physical design process.
This tutorial comprehensively covers the entire physical design process for both 2D and 3D ICs. It starts with an in-depth introduction to the fundamental concepts and basic algorithms in physical design, including different floorplanning strategies, placement and routing algorithms, clock tree synthesis methods, and timing analysis techniques. It also explores the latest research results in 3D IC physical design. By the end of this tutorial, attendees will have a solid understanding of the VLSI physical design process, and be acquainted with the challenges and opportunities in the research frontier for both 2D and 3D IC designs.
Tutorial Speakers
Hailong Yao
Hailong Yao is a second-level full professor at the School of Computer and Communication Engineering, University of Science and Technology Beijing. He received the Ph.D. degree in computer science and technology from Tsinghua University, Beijing, China, in 2007. From 2007 to 2009, he was a Postdoctoral Research Scholar with the Department of Computer Science and Engineering, University of California at San Diego, La Jolla, CA, USA. He served as Assistant and Associate Professor with the Department of Computer Science and Technology, Tsinghua University from 2009 to 2022. Since 2023, he has been a full Professor with the School of Computer and Communication Engineering, University of Science and Technology Beijing, Beijing, China. His research interests include computer-aided design for ASICs, chiplets, and microfluidic biochips. He has published over 100 academic papers in the EDA field, including more than 20 papers in the CCF-A class TCAD journal and DAC conference. He received several Best Paper Award (Nominations) at ICCAD, SASIMI, GLSVLSI, etc. He was awarded the First Prize for Wu Wenjun Artificial Intelligence Science and Technology Award (Technological Invention Award) in 2022 (the first accomplished person). He serves as the Chair of VLSI Physical Implementation Sub-committee in Ecosystem Development Accelerator of EDA (EDA2) (https://www.eda2.com/), Standing Committee Member of CCF VLSI Design committee. He serves as an editorial board member of ACM Transactions on Design Automation of Electronic Systems (TODAES), and has served as TPC member of domestic and international conferences in the EDA field (such as DAC, ICCAD, DATE, ASPDAC, ISEDA, etc.) for more than 50 times. He is a senior Member of IEEE.
Yuanqing Cheng
Yuanqing Cheng is a tenured associate professor of the School of Integrated Circuit and Engineering, Beihang University, Beijing, China. He received his Ph.D. degree from the Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China. After one year postdoc study at LIRMM, CNRS, France, he joined Beihang University. His research interests include design automation for 3D integrated circuits, as well as low power and architectural optimization of emerging semiconductor technologies. He is currently an editorial board member of Elsevier Integration, the VLSI journal, TPC member of ICCAD/DATE/ASP-DAC/ISEDA, the Treasury of IEEE CEDA Beijing Chapter and a senior member of the IEEE.
Hao Yan
Hao Yan is an Associate Professor at the Southeast University. His research is focused on static timing analysis and optimization. In recent years, he has led projects such as the National Natural Science Fund for Young Scientists, National Key Research and Development Plan, and Provincial Key R&D projects. He has published over 30 papers in the field of Electronic Design Automation (EDA) at conferences such as IEEE/ACM DAC and ICCAD, and received a nomination for the Best Paper at ASP-DAC 2021. He has also guided students to win awards in the Integrated Circuit EDA Design Elite Challenge and the International Timing Analysis Competition (2021&2022 TAU Contest).
AHS: An EDA toolbox for Agile Chip Front-end Design
Abstract: Compared to software design, hardware design is more expensive and time-consuming. This is partly because software community has developed a rich set of modern tools to help software programmers to get projects started and iterated easily and quickly. However, the tools are seriously antiquated and lacking for hardware design. Modern digital chips are still designed manually using hardware description language such as Verilog or VHDL, which requires low-level and tedious programming, debugging, and tuning. In this tutorial, we will introduce AHS: AHS: An EDA toolbox for Agile Chip Front-end Design, which covers new hardware design methodologies and various automation tools. From the design perspective, AHS presents different ways that use different programming interfaces and target different scenarios, including 1) a multi-level hardware intermediate representation based high-level synthesis flow, which uses C and C++ as the programming language; 2) an embedded hardware description language, which uses Rust as the programming language. From the verification perspective, we will present agile simulation and debugging tools, which can check the functional and performance behaviors of the hardware. Hardware design determines the peak performance, while the actual performance is determined by the software. In the end, we will also present a compiler and instrumentation tool for the DNN accelerator.
Tutorial Speakers
Yun (Eric) Liang
Prof Yun (Eric) Liang is currently an Endowed Boya Distinguished Professor in the School of Integrated Circuit and EECS at Peking University. His research interest is at the hardware-software interface with work spanning electronic design automation (EDA), hardware and software co-design, and reconfigurable computing. He has authored over 100 scientific publications in the leading international journals and conferences. His research has been recognized with three Best Paper Awards and six Best Paper Award Nominations. He currently serves as Associate Editor of the ACM Transactions on Embedded Computing Systems (TECS) and ACM Transactions on Reconfigurable Technology and Systems (TRETS). He was the program chair of 30th Annual IEEE International Conference on Application-specific Systems, Architecture and Processors (ASAP) 2019 and the International Conference on Field Programmable Technology (FPT) 2022. He currently serves in the program committees in the premier conferences including DAC, ICCAD, FPGA, FCCM, HPCA, MICRO, ASPDAC, etc.
Jingwen Leng
Jingwen Leng is a full professor at the Department of Computer Science and Engineering at Shanghai Jiao Tong University. His research direction is the intelligent computer system design for the artificial intelligence, with the focus on performance, energy efficiency, and reliability. He has received multiple grants from National Science Foundation of China and top industrial companies. He has published more than 50 papers in top tier computer architecture conferences and more than 10 domestic/international patents. His work has received best paper award or nomination at venues/conferences including IEEE Micro Top Picks, DAC, and PACT. He was also awarded the DAMO Young Fellow from Alibaba.
Formal Verification for EDA
Abstract: In the realm of electronic design automation (EDA), the exponential growth in chip complexity—driven by advanced nodes, billions of transistors, and safety-critical applications—demands verification methodologies that transcend traditional simulation. While simulations validate observed scenarios, they cannot exhaustively check all possible states, leaving risks of undetected errors. Formal verification fills this gap, offering exhaustive analysis and becoming indispensable in modern IC development. Two pillars of formal verification—equivalence checking and model checking—play pivotal roles in ensuring functional integrity and reliability.
In this tutorial, we have planned two talks to introduce techniques of equivalence checking and model checking. Our first talk will introduce the fundamentals and recent advancements for constraint solving and combinatorial equivalence checking, with a particular interest in parallel algorithms, noting that constraint solving is the underlying engines for both equivalence checking and model checking. Following this, our second talk will provide an in-depth exploration of model checking, including fundamentals and challenges, as well as some prospects.
Tutorial Speakers
Shaowei Cai
Shaowei Cai is a Professor at Institute of Software, Chinese Academy of Sciences. His research interests include constraint solving and formal verification. He has received the Best Paper Award at SAT 2021 and CP 2024 and Distinguihsed Paper Award at CAV 2024. He has won 10+ gold medals in SAT competitions, and won the Largest Leading Award and Largest Contribution Award 6 times in SMT Competitions, ranked 1st in more than 20 categories. He has led a team working on EDA formal verification tools, including equivalence checking and model checking. His solvers have been used in several EDA companies and also in software verification industries. The formal tools in his group have been used to successfully identy and fix bugs in XiangShan, which is a high-performance RISC-V multi-core processor
Hongce Zhang
Hongce Zhang is an Assistant Professor in Microelectronics Thrust at Hong Kong University of Science and Technology (Guangzhou). He received his PhD from Princeton University in 2021. He is a co-developer of the Pono model checker and his work on instruction-level abstraction (ILA) received the 2020 ACM TODAES best paper award. He has also served as the chair of IEEE Council on EDA, Guangzhou Chapter in 2023 and the program committee member for DAC, CAV, ICCD, FMCAD, GLSVLSI etc.
LLM Applications in EDA
Talk List:
Talk 1: Large Language Model in EDA
Talk 2: Scaling Up the Hardware Design Capability of LLMs
Talk 3: Machine Learning and Formal Verification Joining Hands
Tutorial Speakers
Bei Yu
Prof. Bei Yu is currently an Associate Professor in the Department of Computer Science and Engineering, The Chinese University of Hong Kong. He has served as TPC Chair of ACM/IEEE Workshop on Machine Learning for CAD, and in many journal editorial boards and conference committees. He received eleven Best Paper Awards from ICCAD 2024 & 2021 & 2013, IEEE TSM 2022, DATE 2022, ASPDAC 2021 & 2012, ICTAI 2019, the VLSI Journal in 2018, ISPD 2017, SPIE Advanced Lithography Conference 2016, and eight ICCAD/ISPD contest awards. He received IEEE CEDA Ernest S. Kuh Early Career Award in 2021, ACM SIGDA Meritorious Service Award in 2022, DAC Under-40 Innovator Award in 2024, and Hong Kong RGC Research Fellowship Scheme (RFS) Award in 2024.
Ying Wang
Dr. Ying Wang is an professor in Institute of Computing Technology, Chinese Academy of Sciences, Beijing, and his current research interest includes the chip design automation, reliable computer architecture and memory system. He has published over 100 papers on IEEE/ACM conferences and journals, including TC, DAC, MICRO, HPCA and ICCAD. He has received several awards from international conferences, including the championship of IEEE LPIRC contest at DAC 2016, the championship of the System Design Contest at DAC 2018, 2024 IEEE Top Picks on IC testability and reliability, the Best Paper Award at ITC-Asia, GLSVLSI and ICCD. He is also the recipient of IEEE/ACM DAC under 40 innovator at 2021.
Ansuman Banerjee
Ansuman Banerjee is currently working as a Professor at the Advanced Computing and Microelectronics Unit, Indian Statistical Institute Kolkata since 2010. He received his Bachelor in Engineering from Jadavpur University, and M.S. and Ph.D. degrees from the Indian Institute of Technology Kharagpur -- all in Computer Science. He has an experience of over 20 years working on different projects in Formal Verification for a wide variety of application areas.
AI-Driven Breakthroughs in Next-Generation Circuit Simulation and Reliability
Abstract: Simulation plays a pivotal role in modern IC design, from transistor-level SPICE analysis to electromigration (EM), IR-drop, and thermal reliability checks. As integrated circuits continue to grow in scale and complexity, driven by advanced 3D integration, simulation and reliability challenges become increasingly intricate. Fast and accurate simulation techniques have thus become indispensable for ensuring performance, reliability, and time-to-market. This tutorial gathers experts from academia and industry to explore cutting-edge AI-driven and advanced simulation methodologies that address these pressing issues.
The first part of the tutorial focuses on LLM-Driven Post-layout Simulation Acceleration, where we demonstrate how large language models (LLMs) can identify parasitic-sensitive nodes in circuits. This information is then used to apply targeted RC reductions in the post-layout simulation phase, significantly accelerating simulation times while maintaining accuracy.
Next, we explore the critical issue of reliability in next-generation ICs with Electromigration-Thermal Co-Simulation. As heterogeneous integration in 3D ICs continues to push the limits of performance, electromigration-thermal coupling has emerged as a major reliability bottleneck. This talk systematically examines the challenges of implementing effective EM-thermal co-simulation methodologies to address these issues.
The final presentation introduces ISPT-Net, a novel approach to transient analysis in large-scale circuits. By leveraging irregular sequential prediction transformers, ISPT-Net provides accurate initial solutions for Newton-Raphson (NR) methods and improves LTE estimation, drastically reducing backward stepping in simulations. This results in significant computational savings and increased accuracy, especially in real-world industrial SPICE simulations.
This tutorial will provide valuable insights into how AI-driven solutions are transforming circuit simulation and reliability analysis, offering attendees a glimpse into the future of automated, high-performance simulation workflows for advanced IC designs.
Tutorial Speakers
Zhou Jin
Prof. Zhou Jin is currently a ZJU100 Young Professor at Zhejiang University. She received her Bachelor’s degree from Nanjing University in 2010, followed by her Master’s and Ph.D. degrees from Waseda University, Japan, in 2012 and 2015, respectively. From 2017 to 2022, she served as an Assistant Professor at the Super Scientific Software Laboratory, China University of Petroleum, Beijing, and was later promoted to Associate Professor from 2023 to 2024. Her research interests primarily include AI-driven and GPU-accelerated transistor-level nonlinear circuit simulation, as well as hardware-software co-design for linear algebra applications. She has received multiple awards, such as the Best Paper Award at SC’23, Best Paper Award Finalist at SC’24, Honorable Paper Award at ISEDA’23, and the IEEJ Kyushu Branch Award in 2013, etc.
Zhenya Zhou
Mr. Zhenya Zhou is currently a VP of R&D at Huada Empyrean Technology. His research interests include transistor-level circuit simulation, multi-physics analysis, and electromigration (EM) reliability assessment.
Dan Niu
Dan Niu (Member, IEEE) received the Ph.D. degree from the Graduate School of Information, Production and Systems, Waseda University, Japan. He has been an Associate Professor with the School of Automation, Southeast University, Nanjing, China. His research interests include AI for simulation and verification technologies of large-scale nonlinear circuits and systems, and AI for Spatiotemporal Sequence Prediction.